Patents by Inventor Gregory Thomas Ostrowicki

Gregory Thomas Ostrowicki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230102688
    Abstract: In a described example, an apparatus includes: a semiconductor die with a component on a device side surface; a die seal surrounding the component on the device side surface; a package substrate having bond pads on a die side surface; a package substrate seal formed on the die side surface of the package substrate corresponding to the die seal on the semiconductor die; the semiconductor die flip chip mounted on the bond pads of the package substrate with solder joints connecting post connects on the semiconductor die to the bond pads of the package substrate; a mold compound seal formed by the die seal and the package substrate seal; and mold compound covering a portion of the semiconductor die, a portion of the die side of the package substrate, and contacting the mold compound seal, the mold compound spaced from the component.
    Type: Application
    Filed: September 28, 2021
    Publication date: March 30, 2023
    Inventors: Amit Sureshkumar Nangia, Gregory Thomas Ostrowicki
  • Publication number: 20220415824
    Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Inventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
  • Patent number: 11430747
    Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: August 30, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
  • Publication number: 20220246489
    Abstract: A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.
    Type: Application
    Filed: April 18, 2022
    Publication date: August 4, 2022
    Inventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
  • Publication number: 20220208695
    Abstract: A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.
    Type: Application
    Filed: March 4, 2021
    Publication date: June 30, 2022
    Inventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
  • Publication number: 20210296196
    Abstract: A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 23, 2021
    Inventors: Gregory Thomas Ostrowicki, Amit Sureshkumar Nangia
  • Patent number: 9812384
    Abstract: A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first metallic clip (360) has a plate portion (360a) and a ridge portion (360c) bent at an angle from the plate portion. The plate portion is attached to the terminal of the first transistor chip opposite the second transistor chip. The ridge portion extends to the substrate is and is configured as a plurality of parallel straight fingers (360d). Each finger is discretely attached to the substrate using attachment material (361), for instance solder, and operable as a spring-line cantilever to accommodate, under a force lying in the plane of the substrate, elastic elongation based upon inherent material characteristics.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: November 7, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Gregory Thomas Ostrowicki
  • Publication number: 20170250126
    Abstract: A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first metallic clip (360) has a plate portion (360a) and a ridge portion (360c) bent at an angle from the plate portion. The plate portion is attached to the terminal of the first transistor chip opposite the second transistor chip. The ridge portion extends to the substrate is and is configured as a plurality of parallel straight fingers (360d). Each finger is discretely attached to the substrate using attachment material (361), for instance solder, and operable as a spring-line cantilever to accommodate, under a force lying in the plane of the substrate, elastic elongation based upon inherent material characteristics.
    Type: Application
    Filed: November 15, 2016
    Publication date: August 31, 2017
    Inventor: Gregory Thomas Ostrowicki
  • Patent number: 9496208
    Abstract: A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first metallic clip (360) has a plate portion (360a) and a ridge portion (360c) bent at an angle from the plate portion. The plate portion is attached to the terminal of the first transistor chip opposite the second transistor chip. The ridge portion extends to the substrate is and is configured as a plurality of parallel straight fingers (360d). Each finger is discretely attached to the substrate using attachment material (361), for instance solder, and operable as a spring-line cantilever to accommodate, under a force lying in the plane of the substrate, elastic elongation based upon inherent material characteristics.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: November 15, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Gregory Thomas Ostrowicki