Patents by Inventor Gregory Tse

Gregory Tse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200237423
    Abstract: Certain aspects relate to systems, devices and techniques for vessel sealing and cutting. In particular, an instrument is provided that is capable of performing multiple functions, including sealing and cutting. The instrument can be robotically controlled, and can include a shaft, a multi-DOF wrist, and an end effector. The end effector is capable of generating and delivering heat via different energy modalities to perform the various functions at different temperatures.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 30, 2020
    Inventors: Spencer James Witte, Luis Andrade Baez, JR., Christopher Allen Julian, Thomas R. Jenkins, Gregory Tse
  • Publication number: 20070079032
    Abstract: An apparatus may include a Serial General Purpose Input Output (SGPIO) initiator device. The SGPIO initiator device may have terminals to receive parallel input signals. The device may also have parallel-to-serial conversion logic to convert the parallel input signals to a serial stream. The device may further have signal ordering logic. The signal ordering logic may be in communication with the terminals and may be in communication with the parallel-to-serial conversion logic. The signal ordering logic may determine an order in which the parallel input signals are provided in the serial stream. Methods of ordering signals within an SGPIO initiator device and systems having SGPIO initiator devices are also disclosed.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Sailesh Bissessur, Joseph Murray, Brian Skerry, Robert Sheffield, Richard Beckett, Gregory Tse
  • Publication number: 20060156211
    Abstract: A method and system for syndrome generation and data recovery is described. The system includes a recovery device coupled to one or more storage devices to recover data in the storage devices. The recovery device includes a first comparator to generate a first parity factor based on data in one or more of the storage devices, a multiplier to multiply data from one or more of the storage devices with a multiplication factor to generate a product, and a second comparator coupled to the multiplier to generate a second parity factor based at least in part on the product.
    Type: Application
    Filed: December 23, 2004
    Publication date: July 13, 2006
    Inventors: Samantha Edirisooriya, Gregory Tse, Mark Schmisseur, Robert Sheffield
  • Publication number: 20060143358
    Abstract: Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2004
    Publication date: June 29, 2006
    Inventors: Samantha Edirisooriya, Steven Tu, Gregory Tse, Sujat Jamil, David Miner, R. O'Bleness, Hang Nguyen
  • Publication number: 20060136619
    Abstract: Techniques to accelerate block guard processing of data by use of block guard units in a path between a source memory device and an originator of a data transfer request. The block guard unit may intercept the data transfer request and data transferred in response to the data transfer request. The block guard unit may utilize a cache to store information useful to verify block guards associated with the data.
    Type: Application
    Filed: December 16, 2004
    Publication date: June 22, 2006
    Inventors: Samantha Edirisooriya, Gregory Tse, Joseph Murray
  • Publication number: 20050289253
    Abstract: A method and apparatus for a multi-function direct memory access core are described. In one embodiment, the method includes the reading of a direct memory access (DMA) descriptor having associated DMA data to identify at least one micro-command. Once the micro-command is identified, the DMA data is processed according to the micro-command during DMA transfer of the data. In one embodiment, a DMA engine performs an operation on the DMA data in transit within the DMA controller according to the identified micro-command. Hence, by defining a primitive set of micro-commands, the DMA engine within, for example, an input/output (I/O) controller hub (ICH), can be used to perform a large number of complex operations on data when data is passing through the ICH without introducing latency into the DMA transfer. Other embodiments are described and claimed.
    Type: Application
    Filed: June 24, 2004
    Publication date: December 29, 2005
    Inventors: Samantha Edirisooriya, Joseph Murray, Gregory Tse, Vishram Sarurkar, Manish Goel