Abstract: A method of making a semiconductor structure, the method including providing a silicon on insulator (SOI) substrate having a first epitaxial layer and a bulk silicon substrate separated by a buried oxide layer. The method further includes performing a local oxidation of silicon (LOCOS) process in a region of the SOI substrate to at least partially oxidize the first epitaxial silicon layer in the region, and locally etching the SOI substrate in the region to create a trench through the buried oxide layer and to the bulk silicon substrate. The method further includes forming a second epitaxial layer on the bulk silicon substrate in the trench, and forming one or more semiconductor devices in the first and second epitaxial layers.

Abstract: A semiconductor structure includes a semiconductor wafer having one or more semiconductor devices and an inductor attached to an upper surface of said semiconductor wafer. The semiconductor structure further includes a redistribution layer electrically connecting the inductor to at least one of said one or more semiconductor devices.

Abstract: A method of forming a semiconductor structure including forming an inductor on a substrate and forming one or more semiconductor devices in a semiconductor wafer. The method further includes transferring the inductor from the substrate onto the semiconductor wafer, and forming a redistribution layer electrically connecting the inductor to at least one of the one or more semiconductor devices.

Abstract: A semiconductor structure for RF applications comprises: a target substrate; a micro-transfer printed (?TP) gallium nitride (GaN) chiplet on said target substrate, wherein said chiplet comprises a GaN device and a dummy metal layer.

Abstract: A semiconductor structure for RF applications comprises: a first ?TP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.

Abstract: A semiconductor structure includes a semiconductor wafer having one or more semiconductor devices and an inductor attached to an upper surface of said semiconductor wafer. The semiconductor structure further includes a redistribution layer electrically connecting the inductor to at least one of said one or more semiconductor devices.

Abstract: A semiconductor structure for RF applications comprises: a first ?TP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.

Abstract: A semiconductor structure for RF applications comprises: a first ?TP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.

Abstract: A semiconductor structure for RF applications comprises: a target substrate; a micro-transfer printed (?TP) gallium nitride (GaN) chiplet on said target substrate, wherein said chiplet comprises a GaN device and a dummy metal layer.

Abstract: A semiconductor structure for RF applications comprises: a first ?TP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.

Abstract: The present invention relates to a method for forming an electronic device intended to accommodate at least one fully depleted transistor of the FDSOI type and at least one partially depleted transistor of the PDSOI type, from a stack of layers (10) comprising at least one insulating layer (100) topped with at least one active layer (200) made of a semiconductor material, the method comprising at least one step of dry etching and one step of height adjustment between at least two etched elements.

Abstract: The present invention relates to a method for forming an electronic device intended to accommodate at least one fully depleted transistor of the FDSOI type and at least one partially depleted transistor of the PDSOI type, from a stack of layers (10) comprising at least one insulating layer (100) topped with at least one active layer (200) made of a semiconductor material, the method comprising at least one step of dry etching and one step of height adjustment between at least two etched elements.

Abstract: The invention comprises devices and methods for determining residual stress in MEMS devices such as interferometric modulators. In one example, a device measuring residual stress of a deposited conduct material includes a material used to form a MEMS device, and a plurality of disconnectable electrical paths, wherein said plurality of paths are configured to disconnect as a function of residual stress of the material. In another example, a method of measuring residual stress of a conductive deposited material includes monitoring a plurality of signals, each of said plurality of signals being associated with one of a plurality of test structures, said plurality of test structures each being configured to change the associated signal upon being subject to a predetermined amount of residual stress, sensing a change in said plurality of signals, and determining a residual stress level in said material based on the sensed change in the plurality of signals.

Abstract: The invention comprises devices and methods for determining residual stress in MEMS devices such as interferometric modulators. In one example, a device measuring residual stress of a deposited conduct material includes a material used to form a MEMS device, and a plurality of disconnectable electrical paths, wherein said plurality of paths are configured to disconnect as a function of residual stress of the material. In another example, a method of measuring residual stress of a conductive deposited material includes monitoring a plurality of signals, each of said plurality of signals being associated with one of a plurality of test structures, said plurality of test structures each being configured to change the associated signal upon being subject to a predetermined amount of residual stress, sensing a change in said plurality of signals, and determining a residual stress level in said material based on the sensed change in the plurality of signals.

Abstract: A microelectromechanical systems device having an electrical interconnect between circuitry outside the device and at least one of an electrode and a movable layer within the device. At least a portion of the electrical interconnect is formed from the same material as a conductive layer between the electrode and a mechanical layer of the device. In an embodiment, this conductive layer is a sacrificial layer that is subsequently removed to form a cavity between the electrode and the movable layer. The sacrificial layer is preferably formed of molybdenum, doped silicon, tungsten, or titanium. According to another embodiment, the conductive layer is a movable reflective layer that preferably comprises aluminum.