Abstract: Diverse applications from particle physics experiments to lidar are driving cost and current reduction in giga-hertz sampling rate high-resolution data conversion. Multiple imagers captures a single pixel of data and require processing at very high speed. High-bandwidth high-rate signal sampling, analog-to-digital conversion, and transfer of large amounts of data to a digital data acquisition block are required in such systems. Dynamic range, power consumption, and transfer of high-speed, high-bit width data are key implementation challenges. Data acquisition architectures optimized for specific requirements of such systems may facilitate system implementation and reduce overall system cost.

Abstract: Diverse applications from particle physics experiments to lidar are driving cost and current reduction in giga-hertz sampling rate high-resolution data conversion. Multiple imagers captures a single pixel of data and require processing at very high speed. High-bandwidth high-rate signal sampling, analog-to-digital conversion, and transfer of large amounts of data to a digital data acquisition block are required in such systems. Dynamic range, power consumption, and transfer of high-speed, high-bit width data are key implementation challenges. Data acquisition architectures optimized for specific requirements of such systems may facilitate system implementation and reduce overall system cost.

Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.

Abstract: A wireless communications system includes a clock module, a global positioning system (GPS) module, an integrated circuit for a cellular transceiver, and a baseband module. The clock module is configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). The GPS module is configured to operate in response to the first clock reference. The integrated circuit includes a system phase lock loop (PLL) configured to (i) operate in response to the first clock reference, and (ii) generate a corrected clock reference by performing AFC on the first clock reference in response to an AFC signal. The baseband module is configured to (i) operate in response to the first clock reference from the clock module, and (ii) generate the AFC signal.

Abstract: A receiver including a mixer, a clock generator, a plurality of capacitances, a plurality of resistances, and a controller. The mixer includes a plurality of switches. The clock generator is configured to generate clock signals to drive the plurality of switches of the mixer. The plurality of capacitances couples the clock signals to respective inputs of the plurality of switches. The plurality of resistances couples to the respective inputs of the plurality of switches. The controller is configured to output a first signal to the plurality of resistances. The first signal determines one or more attributes of the clock signals. One or more switching characteristics of the plurality of switches of the mixer are based on the one or more attributes of the clock signals.

Abstract: A wireless communications system includes a clock module, a global positioning system (GPS) module, an integrated circuit for a cellular transceiver, and a baseband module. The clock module is configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). The GPS module is configured to operate in response to the first clock reference. The integrated circuit includes a system phase lock loop (PLL) configured to (i) operate in response to the first clock reference, and (ii) generate a corrected clock reference by performing AFC on the first clock reference in response to an AFC signal. The baseband module is configured to (i) operate in response to the first clock reference from the clock module, and (ii) generate the AFC signal.

Abstract: A wireless communications system includes a clock module, a communications module, a receiver module, and a baseband module. The clock module is configured to generate a first clock reference. The communications module is configured to operate in response to the first clock reference and independent of a corrected clock reference. The corrected clock reference is generated by performing automatic frequency correction on the first clock reference according to an automatic frequency correction signal. The receiver module is configured to (i) receive radio frequency signals from a wireless medium, and (ii) in response to the corrected clock reference, generate baseband signals based on the received radio frequency signals. The baseband module is configured to (i) receive the baseband signals, and (ii) in response to a selected one of the first clock reference and the corrected clock reference, generate the automatic frequency correction signal based on the baseband signals.

Abstract: A circuit includes first and second transconductance stages that generate first and second currents, respectively, in response to an input signal. A current combiner circuit selectively couples the first current to a first output, selectively couples the second current to the first output, selectively couples the first current to a second output, and selectively couples the second current to the second output. In response to the first current being coupled to both the first and second outputs, the current combiner circuit couples the second current to both the first and second outputs. In response to the first current being decoupled from the second output, the current combiner circuit decouples the second current from both the first and second outputs. In response to the first current being decoupled from the first output, the current combiner circuit decouples the second current from both the first and second outputs.

Abstract: A transmitter including a first mixer, a first frequency divider to divide a frequency of an input signal to generate a first signal, and a plurality of second frequency dividers to divide the frequency to respectively generate a plurality of second signals, and a control module. In response to the transmitter being turned on, the control module turns on the first frequency divider, turns off the plurality of second frequency dividers, and drives the first mixer with the first signal. Subsequently, in response to determining that a transmit power of the transmitter is to be increased, the control module sequentially turns on and connects each of the plurality of second frequency dividers in parallel to the first frequency divider. Upon a second frequency divider being connected to the first frequency divider, the control module also drives the first mixer using the second signal generated by that second frequency divider.

Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.

Abstract: This disclosure describes techniques for modulating data. In one embodiment, these techniques include receiving an I or Q value, generating a time-shifted sample of a shaped pulse based on the I or Q value, and providing the time-shifted sample to a digital-to-analog converter.

Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.

Abstract: A method for DC offset cancellation includes defining, in a range of possible gain values for operating a direct conversion receiver, multiple sub-ranges of the possible gain values. Multiple DC offset correction values for the respective sub-ranges are stored in a memory. Upon detecting at the receiver that a gain of the receiver has changed from a first sub-range to a second sub-range, DC offset cancellation is initiated based on a DC offset correction value stored for the second sub-range and on a condition relating to past operation in the second sub-range.

Abstract: A wireless communications system includes a clock module, a communications module, a receiver module, and a baseband module. The clock module is configured to generate a first clock reference. The communications module is configured to operate in response to the first clock reference and independent of a corrected clock reference. The corrected clock reference is generated by performing automatic frequency correction on the first clock reference according to an automatic frequency correction signal. The receiver module is configured to (i) receive radio frequency signals from a wireless medium, and (ii) in response to the corrected clock reference, generate baseband signals based on the received radio frequency signals. The baseband module is configured to (i) receive the baseband signals, and (ii) in response to a selected one of the first clock reference and the corrected clock reference, generate the automatic frequency correction signal based on the baseband signals.

Abstract: A system including a filter and a downconverter. The filter is configured to receive, from a node, (i) a first signal and (ii) a second signal, and filter the second signal. The filter includes a first input impedance. The filter comprises a first plurality of switches and a first circuit. The first plurality of switches is configured to communicate with the node. The first plurality of switches is clocked at a first frequency. The first frequency is based on a frequency of the first signal. The first circuit is configured to communicate with an output of the plurality of switches. The first circuit includes a second input impedance. The second input impedance is different than the first input impedance. The downconverter is configured to (i) receive the first signal and (ii) downconvert the first signal. The filter and the downconverter are connected in parallel to the node.

Abstract: A receiver including a mixer configured to generate (i) a first output and (ii) a second output, a first capacitance coupled to the first output, and a second capacitance coupled to the second output, A controller is configured to program (i) the first capacitance and (ii) the second capacitance to a first capacitance value in response to operating the receiver in a first mode, and program (i) the first capacitance and (ii) the second capacitance to a second capacitance value in response to operating the receiver in a second mode. The first capacitance value determines one or more of (i) linearity, (ii) gain, and (iii) noise figure of the receiver in the first mode. The second capacitance value determines one or more of (i) linearity, (ii) gain, and (iii) noise figure of the receiver in the second mode.

Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Abstract: A method includes receiving a signal using a direct conversion receiver, while the receiver is set at a gain that is selected from a range of possible gain values. Multiple DC offset correction values are provided for use by a DC offset cancellation loop, each DC offset correction value being associated with a respective sub-range of the range of the possible gain values. A DC offset correction value is selected from among the multiple DC offset correction values based on the gain to which the receiver is set. A DC offset in the signal is canceled by setting the DC offset cancellation loop to the selected DC offset correction value.

Abstract: A system including a filter and a downconverter. The filter is configured to receive, from a node, (i) a first signal and (ii) a second signal, and filter the second signal. The filter includes a first input impedance. The filter comprises a first plurality of switches and a first circuit. The first plurality of switches is configured to communicate with the node. The first plurality of switches is clocked at a first frequency. The first frequency is based on a frequency of the first signal. The first circuit is configured to communicate with an output of the plurality of switches. The first circuit includes a second input impedance. The second input impedance is different than the first input impedance. The downconverter is configured to (i) receive the first signal and (ii) downconvert the first signal. The filter and the downconverter are connected in parallel to the node.

Abstract: A method includes receiving a signal using a direct conversion receiver, while the receiver is set at a gain that is selected from a range of possible gain values. Multiple DC offset correction values are provided for use by a DC offset cancellation loop, each DC offset correction value being associated with a respective sub-range of the range of the possible gain values. A DC offset correction value is selected from among the multiple DC offset correction values based on the gain to which the receiver is set. A DC offset in the signal is canceled by setting the DC offset cancellation loop to the selected DC offset correction value.