Abstract: A modified Counter Mode encryption technique encrypts data by receiving a seed value, generating a first value from an operation of the seed value and the plaintext; and encrypting the first value using a block encryption cipher to produce ciphertext. The operation may be an exclusive-or operation. The seed value may be a counter value based upon a position of the block of plaintext in a record of plaintext, where the length of the counter value is based upon the length of the block. The counter value may be generated by adding an initialization vector to a product of an index value and a multiplier value, where the multiplier value comprises a randomly-generated value, the index value is based upon the position of the block of plaintext in the record of plaintext, and the length of the initialization vector and the length of the multiplier value are based upon the length of the block.

Abstract: Data error detection comprises storing in a first buffer data to be written to a medium and a first digital signature of the data. If the first digital signature matches a second digital signature of data read from the first buffer, a compressed form of data read from the first buffer is stored in a FIFO. If the first digital signature matches a third digital signature of an uncompressed form of the compressed data, the uncompressed form of the compressed data, a C2 ECC of a first C1 ECC of the uncompressed form of the compressed data, and one or more C1 ECCs comprising the first C1 ECC and a second C1 ECC of the C2 ECC are stored in a second buffer. Success is indicated if the one or more C1 ECCs match corresponding C1 ECCs calculated from data and C1 ECCs read from the second buffer, and if a C1 ECC of the data read from the second buffer and written to a medium matches a C1 ECC of corresponding data read back from the medium.

Abstract: Data error detection comprises storing in a first buffer data to be written to a medium and a first digital signature of the data. If the first digital signature matches a second digital signature of data read from the first buffer, a compressed form of data read from the first buffer is stored in a FIFO. If the first digital signature matches a third digital signature of an uncompressed form of the compressed data, the uncompressed form of the compressed data, a C2 ECC of a first C1 ECC of the uncompressed form of the compressed data, and one or more C1 ECCs comprising the first C1 ECC and a second C1 ECC of the C2 ECC are stored in a second buffer. Success is indicated if the one or more C1 ECCs match corresponding C1 ECCs calculated from data and C1 ECCs read from the second buffer, and if a C1 ECC of the data read from the second buffer and written to a medium matches a C1 ECC of corresponding data read back from the medium.

Abstract: A data detection circuit for a read channel that recovers data encoded as the presence or absence of flux transitions on a magnetic recording medium, compares a current data sample of a read signal with a previous data sample and a threshold to determine whether the previous data sample represents a flux transition. The use of two data samples in the determination of flux transitions provides a more accurate detection of the data than comparing a single data sample to a threshold value. The data detection circuit generates an output data signal having data values based on the determined flux transitions of the data samples.

Abstract: A data detection circuit for a read channel that recovers data encoded as the presence or absence of flux transitions on a magnetic recording medium, compares a current data sample of a read signal with a previous data sample and a threshold to determine whether the previous data sample represents a flux transition. The use of two data samples in the determination of flux transitions provides a more accurate detection of the data than comparing a single data sample to a threshold value. The data detection circuit generates an output data signal having data values based on the determined flux transitions of the data samples.

Abstract: A write equalization circuit that includes a data encoder for producing a binary data signal wherein a 1 is represented by a transition at the start of a bit interval and a 0 is represented by no transition at the start of a bit interval, and a nominal pulse generating circuit for producing nominal equalization pulses respectively synchronized with predetermined 0's in the binary signal. Adjusting circuitry responsive to the binary data signal and the nominal equalization pulses produces a write data signal that includes equalization pulses having a width and location in bit intervals that remain substantially constant with changes in component delays due to changing temperature and voltage, wherein the constant width and location of the equalization pulses are selected to achieve a predetermined suppression characteristic.

Abstract: A write equalization circuit that includes a data encoder for producing a binary data signal wherein a 1 is represented by a transition at the start of a bit interval and a 0 is represented by no transition at the start of a bit interval, an equalization timing generator for generating a start signal indicative of the initial edges of equalization pulses for predetermined 0's in the binary data signal, and a multiple stage delay delay circuit having logic gates implemented in an integrated circuit and responsive to the start signal and a control word for providing equalization pulses of a substantially constant width, wherein the number of stages employed for delay is determined by the control word.