Abstract: In accordance with an embodiment, a circuit includes a plurality of comparators disposed on an integrated circuit, the plurality of comparators having inputs coupled to a monitored power supply line; and a voting circuit having inputs coupled to outputs of the plurality of comparators. An output of the voting circuit is configured to provide a signal indicative of a brown out condition of a power source coupled to the monitored power supply line.

Abstract: The present invention provides a dual mode phase and frequency detector for use with a charge pump and a loop filter. The charge pump is adapted to adjust charging or discharging of the loop filter to adjust a VCO for generating a digital clock. The dual mode phase and frequency detector includes a phase and frequency detector and a first delay element. The phase and frequency detector is arranged to receive the VCO clock for tracking a reference clock signal. The phase and frequency detector generates control signals in response to the VCO clock and the reference clock signal. The control signals control charging or discharging of a loop filter in a DLL when the phase and frequency detector is operating in a phase and frequency detector mode. The first delay element is coupled to receive one of the control signals from the phase and frequency detector for generating an auxiliary control signal in response to the VCO clock.

Abstract: In accordance with the present invention, an auto-biased cascode current circuit capable of improved range in headroom is disclosed. In one embodiment, the current circuit includes a current mirror and a bias circuit, where the current mirror contains a reference leg and an output leg. A reference current flows within the reference leg. Included in the output leg is an output terminal, a first output transistor and a second output transistor. The output terminal operates at an output potential. The bias circuit regulates the reference leg of the current mirror such that the output potential is substantially equal to a drain-to-source saturation voltage of the first output transistor plus a drain-to-source saturation voltage of the second output transistor plus a predetermined overdrive voltage. The predetermined overdrive voltage is a design parameter which is less than a threshold voltage.