Abstract: Digital counter register stages are constructed as two-to-one mux registers, each employing a multiplexer stage having first, second, and third inputs and an output connected to the switching signal input of a D-type flip-flop, whose Q output comprises a first input to the multiplexer stage. An inverter buffer is associated with each register stage and has an input connected to the output of said D-type flip-flop and an output connected to the second input of the multiplexer stage and fed forward to a NOR gate associated with each subsequent register stage. The output of the NOR gate comprises the third input to the multiplexer stage of the associated register stage.

Abstract: A high-speed data register for storing a series of data values received at a high-speed clock rate and including a first set of pipelined latches and a second set of pipelined latches. Control circuitry loads the received data values alternately into said first set of latches and said second set of latches from an input or "last" register, which stores the last data value received by the data register. Data values thus enter the last register at the high-speed clock rate but are loaded into each of the first and second set of pipelined latches at one-half that rate.