Patents by Inventor Greja Johanna Adriana Maria Verheijden

Greja Johanna Adriana Maria Verheijden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10171007
    Abstract: A method includes providing a substrate having a first sacrificial oxide region, the substrate comprising a first interconnect layer, the first interconnect layer comprising the first sacrificial oxide region. The method further includes covering the first sacrificial oxide region with a first porous layer being permeable to a vapor hydrofluoric acid (HF) etchant and selectively etching the first sacrificial oxide region through the first porous layer using the vapor HF etchant.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Publication number: 20180109203
    Abstract: A method includes providing a substrate having a first sacrificial oxide region, the substrate comprising a first interconnect layer, the first interconnect layer comprising the first sacrificial oxide region. The method further includes covering the first sacrificial oxide region with a first porous layer being permeable to a vapor hydrofluoric acid (HF) etchant and selectively etching the first sacrificial oxide region through the first porous layer using the vapor HF etchant.
    Type: Application
    Filed: December 19, 2017
    Publication date: April 19, 2018
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Patent number: 9859818
    Abstract: A micro-device includes a substrate with a cavity. The cavity is covered with a porous layer that is permeable to vapor hydrofluoric acid (HF) etchant. The micro-device comprises a Microelectromechanical Systems (MEMS) device with a component that is moveable in operational use of the MEMS device. The component is arranged within the cavity.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: January 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Publication number: 20150091411
    Abstract: A micro-device includes a substrate with a cavity. The cavity is covered with a porous layer that is permeable to vapor hydrofluoric acid (HF) etchant. The micro-device comprises a Microelectromechanical Systems (MEMS) device with a component that is moveable in operational use of the MEMS device. The component is arranged within the cavity.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 2, 2015
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Patent number: 8906729
    Abstract: The invention relates to a micro-device with a cavity, the micro-device comprising a substrate, the method comprising steps of: A) providing the substrate, having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant, and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity, i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Patent number: 8872359
    Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element (12). A sidewall (20) is formed around the MEMS device element, and a sacrificial layer (14) is formed over the device element and within the sidewall. A package cover layer (16) is provided over the sacrificial layer, and the sacrificial layer is removed. This method provides additional sidewalls to the cap provided over the MEMS device. These additional sidewalls can then be deposited by a different process and be formed of a different material to the top part of the package cover layer. The sidewalls can prevent reflow of the sacrificial layer and improve the sealing properties of the sidewalls.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventors: Bart Van Velzen, Hans Van Zadelhoff, Greja Johanna Adriana Maria Verheijden
  • Patent number: 8426928
    Abstract: Disclosed is a device comprising a substrate carrying a microscopic structure in a cavity capped by a capping layer including a material of formula SiNxHy, wherein x>1.33 and y>0. A method of forming such a device is also disclosed.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: April 23, 2013
    Assignee: NXP B.V.
    Inventors: Johannes van Wingerden, Greja Johanna Adriana Maria Verheijden, Gerhard Koops, Jozef Thomas Martinus van Beek
  • Patent number: 8367552
    Abstract: The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material on top thereof, depositing a protection layer on top of the dielectric material, depositing a sacrificial layer on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer in the opening and on the sacrificial layer, depositing metal material on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: February 5, 2013
    Assignee: NXP B.V.
    Inventors: Roel Daamen, Viet Nguyen Hoang, Romano Julma Oscar Maria Hoofman, Greja Johanna Adriana Maria Verheijden
  • Patent number: 8330238
    Abstract: A method of packaging a micro electro-mechanical structure comprises forming said structure on a substrate; depositing a sacrificial layer over said structure; patterning the sacrificial layer; depositing a SIPOS (semi-insulating polycrystalline silicon) layer over the patterned sacrificial layer; treating the SIPOS layer with an etchant to convert the SIPOS layer into a porous SIPOS layer, removing the patterned sacrificial layer through the porous layer SIPOS to form a cavity including said structure; and sealing the porous SIPOS layer. A device including such a packaged micro electro-mechanical structure is also disclosed.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: December 11, 2012
    Assignee: NXP B.V.
    Inventors: Johannes van Wingerden, Wim van den Einden, Harold H. Roosen, Greja Johanna Adriana Maria Verheijden, Gerhard Koops, Didem Ernur, Jozef Thomas Martinus van Beek
  • Patent number: 8310053
    Abstract: A micro-device with a cavity, the micro-device including a substrate. A method of forming the micro-device includes the steps of: A) providing the substrate having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant; and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity , i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: November 13, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Patent number: 8273653
    Abstract: A method of packaging a micro electromechanical structure is disclosed. The method comprises the steps of forming the structure on a substrate, depositing a sacrificial layer over the structure, patterning the sacrificial layer, depositing a porous layer over the patterned sacrificial layer, removing the patterned sacrificial layer through the porous layer, treating the porous layer with a plasma and depositing a capping layer over the plasma-treated porous layer. The plasma treatment step ensures that the capping layer material cannot enter the cavity formed by the removal of the sacrificial layer through the porous layer. A device formed by this method is also disclosed.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Publication number: 20110186941
    Abstract: Disclosed is a device comprising a substrate carrying a microscopic structure in a cavity capped by a capping layer including a material of formula SiNxHy, wherein x>1.33 and y>0. A method of forming such a device is also disclosed.
    Type: Application
    Filed: October 29, 2010
    Publication date: August 4, 2011
    Applicant: NXP B.V.
    Inventors: Johannes van WINGERDEN, Greja Johanna Adriana Maria VERHEIJDEN, Gerhard KOOPS, Jozef Thomas Martinus van BEEK
  • Publication number: 20110175178
    Abstract: A method of packaging a micro electro-mechanical structure comprises forming said structure on a substrate; depositing a sacrificial layer over said structure; patterning the sacrificial layer; depositing a SIPOS (semi-insulating polycrystalline silicon) layer over the patterned sacrificial layer; treating the SIPOS layer with an etchant to convert the SIPOS layer into a porous SIPOS layer, removing the patterned sacrificial layer through the porous layer SIPOS to form a cavity including said structure; and sealing the porous SIPOS layer. A device including such a packaged micro electro-mechanical structure is also disclosed.
    Type: Application
    Filed: November 23, 2010
    Publication date: July 21, 2011
    Applicant: NXP B.V.
    Inventors: Johannes van WINGERDEN, Wim van den EINDEN, Harold H. ROOSEN, Greja Johanna Adriana Maria VERHEIJDEN, Gerhard KOOPS, Didem ERNUR, Jozef Thomas Martinus van BEEK
  • Publication number: 20110147944
    Abstract: Manufacturing a damascene structure involves: forming a sacrificial layer (20) on a substrate (10) to protect an area around a recess (30) for the damascene structure, forming a barrier layer (40) in the recess, and in electrical contact with the sacrificial layer, forming the damascene structure (50) in the recess, and planarising. During the planarising the sacrificial layer reacts electrochemically with the barrier layer or with the damascene structure. This can alter a relative rate of removal of the damascene structure and the sacrificial layer so as to reduce dishing or protrusion of the damascene structure, and reduce copper residues, and reduce barrier corrosion. The barrier layer can be formed by ALCVD. The barrier material being one or more of WCN and TaN. The sacrificial layer can be TaN, TiN or W.
    Type: Application
    Filed: November 2, 2005
    Publication date: June 23, 2011
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Viet Nguyen Hoang, Greja Johanna Adriana Maria Verheijden
  • Patent number: 7736948
    Abstract: Individual devices (100) are locally attached to a carrier substrate (10), so that they can be removed therefrom individually. This is achieved through the use of a patterned release layer, particularly a layer that is removable through decomposition into gaseous or vaporized decomposition products. The mechanical connection between the carrier substrate (10) and the individual devices (100) is provided by a bridging portion (43) of an adhesion layer (40).
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: June 15, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Ronald Dekker, Greja Johanna Adriana Maria Verheijden, Theodorus Martinus Michielsen, Carel Van Der Poel, Cornelis Adrianus Henricus Antonius Mutsaers
  • Publication number: 20100006957
    Abstract: A method of packaging a micro electromechanical structure is disclosed. The method comprises the steps of forming the structure on a substrate, depositing a sacrificial layer over the structure, patterning the sacrificial layer, depositing a porous layer over the patterned sacrificial layer, removing the patterned sacrificial layer through the porous layer, treating the porous layer with a plasma and depositing a capping layer over the plasma-treated porous layer. The plasma treatment step ensures that the capping layer material cannot enter the cavity formed by the removal of the sacrificial layer through the porous layer. A device formed by this method is also disclosed.
    Type: Application
    Filed: June 3, 2009
    Publication date: January 14, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Greja Johanna Adriana Maria VERHEIJDEN, Roel Daamen, Gerhard Koops
  • Publication number: 20090267166
    Abstract: The invention relates to a micro-device with a cavity (50), the micro-device comprising a substrate (10, 110), the method comprising steps of: A) providing the substrate (10, 110), having a surface and comprising a sacrificial oxide region (20, 107, 115) at the surface ( ); B) covering the sacrificial oxide region (20, 107, 115) with a porous layer (40, 114, 124) being permeable to a vapor HF etchant (100), and C) selectively etching the sacrificial oxide region (20, 107, 115) through the porous layer (40, 114, 124) using the vapor HF etchant (100) to obtain the cavity (50). This method may be used in the manufacture of various micro-devices with a cavity (50), i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.
    Type: Application
    Filed: April 22, 2009
    Publication date: October 29, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Patent number: 7589425
    Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises providing a substantially planar layer having a first metal layer, depositing a via level dielectric layer, patterning the via level dielectric layer, at least partly etching the via level dielectric layer, depositing a disposable layer on the at least partly etched via level dielectric layer, patterning the disposable layer, depositing a second metal layer, planarizing second metal layer, depositing permeable dielectric layer after planarizing the second metal layer, and removing the disposable layer through the permeable dielectric layer to form air gaps.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: September 15, 2009
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Roel Daamen, Greja Johanna Adriana Maria Verheijden
  • Publication number: 20080315440
    Abstract: Individual devices (100) are locally attached to a carrier substrate (10), so that they can be removed therefrom individually. This is achieved through the use of a patterned release layer, particularly a layer that is removable through decomposition into gaseous or vaporized decomposition products. The mechanical connection between the carrier substrate (10) and the individual devices (100) is provided by a bridging portion (43) of an adhesion layer (40).
    Type: Application
    Filed: November 3, 2006
    Publication date: December 25, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
    Inventors: Ronald Dekker, Greja Johanna Adriana Maria Verheijden, Theodorus Martinus Michielsen, Carel Van Der Poel, Cornelis Adrianus Henricus Antonius Mutsaers
  • Patent number: 7361453
    Abstract: A method of manufacturing a semiconductor device with precision patterning is disclosed. A structure of a small dimension is created in a material, such as a semiconductor material, using a first and a second pattern, the patterns being identical but displaced over a distance with respect to each other. Two mask layers are used, wherein the first pattern is etched into the upper mask layer with a selective etch, and the second pattern is created on the upper mask layer or on the lower mask layer at locations where the upper mask layer has been removed. A part of the lower mask layer and/or the upper mask layer is etched according to the second pattern, resulting in a mask formed by remaining parts of the lower and upper mask layers, the mask having a structure with a dimension determined by a displacement of the second pattern with respect to the first pattern.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: April 22, 2008
    Assignees: Interuniversitair Microelektronica Centrum vzw (IMEC), Koninklijke Philips Electronics
    Inventors: Greja Johanna Adriana Maria Verheijden, Pascal Henri Leon Bancken, Johannes van Wingerden