Patents by Inventor Griffin John Kennedy
Griffin John Kennedy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136192Abstract: Provided herein are low resistance metallization stack structures for 3D-NAND applications and related methods of fabrication. In some embodiments, thin metal oxynitride nucleation layers are deposited on dielectric material followed by deposition of a pure metal conductor using process conditions that increase non-molybdenum component element content at the oxynitride-dielectric interface. Certain embodiments of the methods described below convert less than all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: February 18, 2022Publication date: April 25, 2024Inventors: Lawrence Schloss, Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Sang-Hyeob Lee, Patrick van Cleemput, Sanjay Gopinath
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Publication number: 20230290680Abstract: Provided herein are methods and apparatuses for forming metal films such as tungsten (W) and molybdenum (Mo) films on semiconductor substrates. The methods involve forming a reducing agent layer, then exposing the reducing agent layer to a metal precursor to convert the reducing agent layer to a layer of the metal. In some embodiments, the reducing agent layer is a silicon- (Si-) and boron- (B-) containing layer. The methods may involve forming the reducing agent layer at a first substrate temperature, raising the substrate temperature to a second substrate temperature, and then exposing the reducing agent layer to 10 the metal precursor at the second substrate temperature. The methods may be used to form fluorine-free tungsten or molybdenum films in certain embodiments. Apparatuses to perform the methods are also provided.Type: ApplicationFiled: May 1, 2023Publication date: September 14, 2023Inventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Michal Danek, Shruti Vivek Thombare, Patrick A. van Cleemput, Gorun Butail
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Publication number: 20220356579Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Joshua COLLINS, Griffin John KENNEDY, Hanna BAMNOLKER, Patrick A. VAN CLEEMPUT, Seshasayee VARADARAJAN
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Publication number: 20220223471Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: ApplicationFiled: January 31, 2022Publication date: July 14, 2022Inventors: Shruti Vivek THOMBARE, Raashina HUMAYUN, Michal DANEK, Chiukin Steven LAI, Joshua COLLINS, Hanna BAMNOLKER, Griffin John KENNEDY, Gorun BUTAIL, Patrick A. van Cleemput
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Publication number: 20220195598Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: January 27, 2020Publication date: June 23, 2022Inventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Patrick A. van Cleemput, Seshasayee Varadarajan
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Publication number: 20200402846Abstract: Provided herein are methods and apparatuses for forming metal films such as tungsten (W) and molybdenum (Mo) films on semiconductor substrates. The methods involve forming a reducing agent layer, then exposing the reducing agent layer to a metal precursor to convert the reducing agent layer to a layer of the metal. In some embodiments, the reducing agent layer is a silicon- (Si-) and boron- (B-) containing layer. The methods may involve forming the reducing agent layer at a first substrate temperature, raising the substrate temperature to a second substrate temperature, and then exposing the reducing agent layer to the metal precursor at the second substrate temperature. The methods may be used to form fluorine-free tungsten or molybdenum films in certain embodiments. Apparatuses to perform the methods are also provided.Type: ApplicationFiled: November 19, 2018Publication date: December 24, 2020Applicant: Lam Research CorporationInventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Michal Danek, Shruti Vivek Thombare, Patrick van Cleemput, Gorun Butail
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Publication number: 20200365456Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: ApplicationFiled: July 27, 2020Publication date: November 19, 2020Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick van Cleemput
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Patent number: 10777453Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: GrantFiled: November 6, 2019Date of Patent: September 15, 2020Assignee: Lam Research CorporationInventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
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Publication number: 20200075403Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
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Patent number: 10510590Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: GrantFiled: April 9, 2018Date of Patent: December 17, 2019Assignee: Lam Research CorporationInventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
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Publication number: 20180294187Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: ApplicationFiled: April 9, 2018Publication date: October 11, 2018Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput