Abstract: A method for testing a chip includes writing, by a built-in self-test (BIST) circuit of the chip, a first row of a memory of the chip with a first set of values and reading, by the BIST circuit, a second row of the memory a first plurality of times. The second row is adjacent to the first row. The method also includes reading, by the BIST circuit, the first row to extract a second set of values from the first row and based on determining that at least one of the second set of values differs from a corresponding one of the first set of values, designating the first row as a vulnerable row.

Abstract: A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In-system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.

Abstract: A system including a user interface, a memory, and a processor configured to perform operations including receiving memory scrambling information including address scrambling information and data scrambling information, and associating one or more address bus bits of a plurality of address bus bits with an address grouping of a plurality of address groupings based on the address scrambling information is disclosed. In an embodiment, the address grouping corresponds to at least one address segment of a plurality of address segments. The operations include determining an error correction code for the at least one address segment that includes one or more address check bits. The operations include generating a physical layout of memory components based on the memory scrambling information. The memory components include at least one of the plurality of address bus bits, and the one or more address check bits.

Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.

Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.

Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.

Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.