Abstract: A very long linear input array capable of acquiring long series of acquisition data is achieved by breaking the long linear array into a series of sub-arrays, each enabled by a "global" set of enable signals. The individual cells of the local arrays are addressed by local x-y enable signals. This arrangement permits the acquisition of very long record lengths, without sacrificing the quality of other aspects of the acquisition process to excess capacitance.

Abstract: A first comparison circuit compares an internally generated clock signal with a reference signal and produces a first error signal in response to timing differences between rising edges of the clock signal and the reference signal. A second comparison circuit compares the internally generated clock signal with the reference signal and produces a second error signal in response to timing differences between falling edges of the clock signal and the reference signal. The first and second error signals are applied to control inputs of a phase shifter chain to control delay in each stage to reduce the timing error with respect to each edge.

Abstract: A circuit modifies a fast-in, slow-out data acquisition system to provide a redundant analog data acquisition cell (aR) that can be substituted for a defective cell without adversely affecting the timing between acquired samples. This circuit includes a plurality of signal acquisition cells (a1-an) including at least one redundant cell arranged in a row, a source of sample and hold clock signals (b1-bn) for the signal acquisition cells, and a corresponding row of demultiplexers (D1-Dn). Each acquisition cell has an analog signal input and a sample and hold clock signal input that determines when the analog signal is to be sampled. The demultiplexers each have a signal input, a select input, and at least two outputs, with the input being coupled to one of the sample and hold clock signals, and the outputs being coupled to the sample and hold clock inputs of two adjacent signal acquisition cells.

Abstract: An improved sample and hold signal generator produces very short delay intervals between successive sample-to-hold transitions that are both collectively and individually adjustable. A plurality of capacitors are charged to a precharge level upon the occurrence of a precharge signal and discharged to the threshold level of a plurality of amplifiers through a plurality of constant current sources upon the occurrence of a discharge signal. When the voltage on a particular capacitor is discharged to the threshold level, the associated amplifier produces a sample-to-hold signal transition and the voltage level of a signal being sampled is stored on a capacitor. In successive cells of the sample and hold generating means the threshold level is reached at incrementally varying delay times that are separated by approximately equal time intervals.

Abstract: A fast, CMOS-based peak detection cell circuit and related methods can be used to determine maximum and minimum excursions of a signal being monitored during the very short intervals between high speed sampling points. Two nodes, "a" and "b", of such a circuit are precharged. Node "a" is then connected to the signal to be monitored. A PMOS transistor, with node "a" on its gate and node "b" on its drain, then causes a capacitance at node "b" to discharge to the voltage level of node "a" plus a constant offset voltage. Node "b" thus tracks downward excursions of the signal to be monitored, but not upward ones. Therefore, the voltage level at node "b" at the end of the acquisition interval is a function of the lowest voltage level assumed by the signal. A trio of such minimum detection cell circuits can be used together to find minimum and maximum behaviors of a differential complementary pair of signals.

Abstract: A multi-channel analog-to-digital converter includes a counter (20) and a plurality of analog-to-digital conversion cells (10), each of which contain incremental discharge means (11-16) that store a charge proportional to the voltage value of an analog input signal and discharge that charge in increments upon the occurrence of the clock signal, also producing an active signal after the charge has been stored and before the incremental discharge is complete. A register (17) receives a count signal from the counter (20) and stores its value when the active signal goes inactive. A multiplexer (18) selects among the outputs of the plurality of analog-to-digital conversion cells (10) and supplies the selected output as a digital output signal.

Abstract: A FISO analog signal acquisition system includes a plurality of CCD arrays (20a-20d), with each array containing a plurality of CCD serial registers (22). Each serial register (22) has a first cell (23) and a large number of additional cells (24) coupled in series with the first cell (24), with acquired samples being transferred along the string of additional cells (24) according to a clock signal having two or more phases, with each CCD array (20a-20d) operating in response to a set of clock signals having a different phase (P1,P2,/P1,/P2). A tapped delay line (10), or other similar hold signal generating means, produces a plurality of closely spaced-in-time sequential hold signals in response to a master hold signal. In response to each one of the hold signals, a CMOS transistor (Q.sub.x) briefly connects an associated first cell (23) to the signal to be sampled so that a series of closely spaced-in-time samples of the signal are acquired.

Abstract: An analog acquisition system includes an array of analog capture cells for capturing and storing a signal on an analog bus. Each capture cell in the array may be sequentially selected for sampling the signal at successive sample times. Timing for selecting a row of the analog memory array is provided by a slow shift register and timing for selecting a capture cell within the row of the analog memory array is provided by a fast tapped delay line. Additional circuitry is provided for controlling the delay of the tapped delay line such that total delay is equal to the time the slow shift register takes to transfer from one row to the next.

Abstract: An accurate delay generator circuit for delaying the rising and falling edge of an input signal includes: a current switch having an input for receiving the input signal, first and second current inputs, and a current output; a p-channel transistor coupled to the first current input of the current switch; a first threshold voltage generator coupled to the gate of the p-channel transistor for generating a voltage equal to twice a p-channel threshold voltage with respect to VDD; an n-channel transistor coupled to the second current input of the current switch; a second threshold voltage generator coupled to the gate of the n-channel transistor for generating a voltage equal to twice an n-channel thresold voltage with respect to ground; a capacitor coupled to the output of the current switch; and an output inverter stage coupled to the output of the current switch for providing the delayed input signal.

Abstract: A serial dynamic memory shift register is configured in the form of an array of dynamic memory cells. Each dynamic memory cell is coupled to a column data bus and is addressed by an individual row command, and the data from the dynamic memory cells are transferred serially from the cells via a temporary latch. The dynamic memory cells and the temporary latch form a subarray, and a plurality of subarrays connected in series form a one-bit slice. A plurality of one-bit slices connected in parallel to receive the multiple bits of a data word in parallel forms a one-word slice. Each one-word slice has an data input latch to transfer data from an input data bus to the one-word slice, and an data output latch to transfer data from the one-word slice to an output data bus.

Abstract: The present invention provides a vertical punch-through cell comprising a silicon substrate, an epitaxial silicon layer overlying the substrate, an N+ buried column line formed at the interface between the substrate and the epitaxial layer, an N+ diffusion region formed above and spaced apart from the buried column line at the surface of the epitaxial layer, a field oxide layer formed over the epitaxial layer and having an contact opening formed therein over the N+ diffusion region, a polysilicon layer formed on the surface of the field oxide layer to extend through the contact opening to make contact with the N diffusion region, a layer of dielectric material formed over the polysilicon layer, and a layer of conductive material formed over the dielectric material.

Abstract: A refresh cell of the type utilized for recharging or "refreshing" data stored in a storage element of a random access memory includes a first field effect transistor (FET) having its drain connected to a supply voltage, its source connected to the drain of a second FET and its gate connected to a first side of a capacitor. The second FET has its drain connected to the source of the first FET, its source connected to a column line of a random access memory and its gate connected to receive a row line signal from the random access memory. The capacitor has its first side connected both to the gate of the first FET and to a first side of a diffused resistive element. The second side of the capacitor is connected to receive a pump signal. The second end of the nonlinear resistor is connected to the source-drain interconnection of the two FETs.

Abstract: The present invention provides a voltage regulator for generating a controlled voltage for an electrical circuit. The voltage regulator comprises a first field effect transistor (FET) having its drain connected to a first node, its source connected to ground and its gate connected to its source. A resistor is connected between a supply voltage and the first node. A second FET has its source connected to the first node and its drain and gate commonly connected to a second node. A third FET has its drain connected to the supply voltage, its source connected to the second node and its gate connected to the interconnection between the resistor and the drain of the first FET. A fourth FET has its drain connected to the supply voltage, its gate connected to the second node and its source connected to provide an output signal. A fifth FET has its drain connected to the supply voltage, its source connected to the drain of a sixth FET and its gate connected to the first node.

Abstract: This present invention provides a voltage sustainer which eliminates the DC current problems of conventional voltage sustainers. The embodiment of the voltage sustainer of the present invention comprises a first field effect transistor (FET) having its drain connected to a supply voltage and its drain connected to a second FET; a second FET having its drain connected to the source of the first FET, its source connected to an output node and its gate connected to the source of a third FET; a third FET having its source connected to the gate of the second FET and its drain connected to the output node; a first MOS capacitor having one side connected to receive an input signal and its other side connected to the interconnection between the source of the first FET and the drain of the second FET; and a second capacitor having one side connected to receive the input signal and its other side connected to the source of the third FET.