Abstract: An input/output circuit in a receiving mode typically has disabled output buffers as well as other electrical components that provide significant receiver input capacities at high operating frequencies. A detection circuit detects the charging/discharging of the parasitic capacitance and operates a regulating circuit to compensate for the charging/discharging of the parasitic capacitance during rising/falling edges of an input signal, thereby correcting for impedance mismatch and reflection glitches.

Abstract: A drive controller monitors a dynamic condition to determine when a transmission line impedance is to vary. In one embodiment, a specific bit pattern associated with a set of data lines can be monitored by the drive controller. Based upon the dynamic condition, the drive controller will determine whether or not the drive strengths of the output drivers associated with the data lines are to be adjusted. The variance in line is compensated for by independently increasing or decreasing drive strengths at the individual output nodes of the drivers.

Abstract: A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M commands per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data at a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four-times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.

Abstract: A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M command per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.