Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

Abstract: Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the voltages used to program the section of memory (such as the program verify levels for programming data into the cells of the section of memory) may be adjusted. Likewise, when reading data from the section of memory, the read voltages may be adjusted based on the adjusted voltages used for programming. In this way, using the adjusted programming and reading voltages, the effect of program disturb may be reduced.

Abstract: Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the voltages used to program the section of memory (such as the program verify levels for programming data into the cells of the section of memory) may be adjusted. Likewise, when reading data from the section of memory, the read voltages may be adjusted based on the adjusted voltages used for programming. In this way, using the adjusted programming and reading voltages, the effect of program disturb may be reduced.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.

Abstract: In response to a request to read data, the non-volatile memory system identifies the physical block that is storing the requested data. Read parameters associated with the physical block are also identified. The read parameters include bit error rate information. The memory system chooses whether to use a read process with a faster sense time or a read process with a slower sense time based on the bit error rate information and temperature data. The requested data is read from the identified physical block using the chosen read process configured by at least a subset of the read parameters.

Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.

Abstract: A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.

Abstract: A non-volatile storage system includes defect detection and early program termination. The system commences programming of a plurality of non-volatile memory cells, determines that a defect condition exists and, in response to determining that the defect condition exists, terminates the programming of the plurality of memory cells prior to completion of programming.

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.

Abstract: Determining dynamic read levels for memory cells is disclosed. A group of memory cells may be read at a pair of reference levels. Results of reading the group at the pair of reference levels are compared while the group is read at a different reference level. By comparing the results of reading the group at the pair of reference levels while reading the group at a different reference level, time is saved. Note that the reading and comparing can be repeated for other pairs of reference levels. The storage device may determine an adjusted read level based on the comparisons of the results for the different pairs of reference levels. The memory cells may be read at a set of reference levels. A voltage on a word line is not back down to ground between the reads in one aspect, which saves considerable time.

Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.

Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for a read operation, including post-write verify reads. Non-selected word lines that are unwritten are biased with a lower read-pass voltage then is typically used. The determination of the last written word line of a block can be done in a coarse-fine search, where the word lines are divided into a number of zones to find the zone with the last written word line, which is in turn sub-divided for a finer search.

Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for a read operation, including post-write verify reads. Non-selected word lines that are unwritten are biased with a lower read-pass voltage then is typically used. The determination of the last written word line of a block can be done in a coarse-fine search, where the word lines are divided into a number of zones to find the zone with the last written word line, which is in turn sub-divided for a finer search.

Abstract: Systems and methods are provided for acquiring status information from a plurality of memory die. An apparatus is provided that includes a plurality of memory die and a memory controller. The memory controller is configured to broadcast a first status command to the plurality of memory die, receive a first status response concurrently from the plurality of memory die based on the first status command, and send a repair command to one or more of the plurality of memory die in response to the first status response not satisfying first predetermined status criteria.

Abstract: Systems and methods for increasing performance and reducing power consumption of a non-volatile memory system while the system acquires status information from a plurality of memory die are described. The non-volatile memory system may include a plurality of memory die and a system controller for controlling operations performed by each memory die of the plurality of memory die (e.g., read operations, write operations, or erase operations). The system controller may transmit or broadcast a first status command to each memory die of the plurality of memory die and in response simultaneously or concurrently receive one or more sets of status information from each memory die of the plurality of memory die. The status information may include ready/busy status information (e.g., indicating that a memory die is able to receive new data), programming loop count information, and erase loop count information.

Abstract: As memory devices scale down, the controller may use different sets of trim values for read/program/erase operations for different blocks based on the amount of wear a block has experienced. To facilitate this process, when the controller issues series of commands, a set of parameters for the operations are initially transferred into latches that are normally used for user data, after which they are transferred into the registers used to hold the parameters while the operation is performed. This allows for read, write and erase parameters to be updated with minimal time penalty and on the fly, allowing for these trim values to be changed more frequently and without the need to add extra registers on the memory circuit.

Abstract: A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches.