Patents by Inventor Grover C. Davidson
Grover C. Davidson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150113226Abstract: A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.Type: ApplicationFiled: December 5, 2013Publication date: April 23, 2015Applicant: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 8973007Abstract: According to one aspect of the present disclosure, a method and technique for adaptive lock list searching of waiting threads includes determining an average service time for a lock associated with a shared computing resource; determining an average search time for selecting a thread to next receive the lock from a plurality of threads waiting for the lock; summing the average service time and the average search time; applying a search factor to the summed average service time and average search time to obtain a target search time for searching the waiting threads for selecting the next thread for obtaining the lock; determining a quantity of waiting threads to consider for next obtaining the lock based on the target search time and the average search time, the quantity being less than a total quantity of waiting threads; and identifying the next thread to obtain the lock from the quantity.Type: GrantFiled: December 9, 2013Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 8954974Abstract: A system and technique for adaptive lock list searching of waiting threads includes logic executable by a processor to: determine an average service time for a lock associated with a shared computing resource; determine an average search time for selecting a thread to next receive the lock from a plurality of threads waiting for the lock; sum the average service time and the average search time; apply a search factor to the summed average service time and average search time to obtain a target search time for searching the waiting threads for selecting the next thread for obtaining the lock; determine a quantity of waiting threads to consider for next obtaining the lock based on the target search time and the average search time, the quantity being less than a total quantity of waiting threads; and identify the next thread to obtain the lock from the quantity.Type: GrantFiled: November 10, 2013Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 8775749Abstract: Management of a UNIX-style storage pools is enhanced by specially managing one or more memory management inodes associated with pinned and allocated pages of data storage by providing indirect access to the pinned and allocated pages by one or more user processes via a handle, while preventing direct access of the pinned and allocated pages by the user processes without use of the handles; scanning periodically hardware status bits in the inodes to determine which of the pinned and allocated pages have been recently accessed within a pre-determined period of time; requesting via a callback communication to each user process to determine which of the least-recently accessed pinned and allocated pages can be either deallocated or defragmented and compacted; and responsive to receiving one or more page indicators of pages unpinned by the user processes, compacting or deallocating one or more pages corresponding to the page indicators.Type: GrantFiled: June 26, 2013Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20140149675Abstract: An information handling system (IHS) includes an operating system with a release-behind component that determines which file pages to release from a file cache in system memory. The release-behind component employs a history buffer to determine which file pages to release from the file cache to create room for a current page access. The history buffer stores entries that identify respective pages for which a page fault occurred. For each identified page, the history buffer stores respective repage information that indicates if a repage fault occurred for such page. The release-behind component identifies a candidate previous page for release from the file cache. The release-behind component checks the history buffer to determine if a repage fault occurred for that entry. If so, then the release-behind component does not discard the candidate previous page from the cache. Otherwise, the release-behind component discards the candidate previous page if a repage fault occurred.Type: ApplicationFiled: December 11, 2013Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Accapadi, Grover C. Davidson, Dirk Michel, Bret R. Olszewski
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Publication number: 20140149672Abstract: An information handling system (IHS) includes an operating system with a release-behind component that determines which file pages to release from a file cache in system memory. The release-behind component employs a history buffer to determine which file pages to release from the file cache to create room for a current page access. The history buffer stores entries that identify respective pages for which a page fault occurred. For each identified page, the history buffer stores respective repage information that indicates if a repage fault occurred for such page. The release-behind component identifies a candidate previous page for release from the file cache. The release-behind component checks the history buffer to determine if a repage fault occurred for that entry. If so, then the release-behind component does not discard the candidate previous page from the cache. Otherwise, the release-behind component discards the candidate previous page if a repage fault occurred.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mathew Accapadi, Grover C Davidson, II, Dirk Michel, Bret R Olszewski
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Publication number: 20130290666Abstract: Management of a UNIX-style storage pools is enhanced by specially managing one or more memory management inodes associated with pinned and allocated pages of data storage by providing indirect access to the pinned and allocated pages by one or more user processes via a handle, while preventing direct access of the pinned and allocated pages by the user processes without use of the handles; scanning periodically hardware status bits in the inodes to determine which of the pinned and allocated pages have been recently accessed within a pre-determined period of time; requesting via a callback communication to each user process to determine which of the least-recently accessed pinned and allocated pages can be either deallocated or defragmented and compacted; and responsive to receiving one or more page indicators of pages unpinned by the user processes, compacting or deallocating one or more pages corresponding to the page indicators.Type: ApplicationFiled: June 26, 2013Publication date: October 31, 2013Applicant: IBM CORPORATIONInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20130227549Abstract: Systems, methods and computer program products may provide managing utilization of one or more physical processors in a shared processor pool. A method of managing utilization of one or more physical processors in a shared processor pool may include determining a current amount of utilization of the one or more physical processors and generating an instruction message. The instruction message may be at least partially determined by the current amount of utilization. The method may further include sending the instruction message to a guest operating system, the guest operating system having a number of enabled virtual processors.Type: ApplicationFiled: February 23, 2012Publication date: August 29, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Patent number: 8499138Abstract: Management of a UNIX-style storage pools is enhanced by specially managing one or more memory management inodes associated with pinned and allocated pages of data storage by providing indirect access to the pinned and allocated pages by one or more user processes via a handle. Direct access of the pinned and allocated pages by the user processes without use of the handles is prevented. Hardware status bits in the inodes are scanned to determine which pinned and allocated pages have been recently accessed and callback communication to each user process is used to determine which of the least-recently accessed pages can be deallocated, defragmented and compacted.Type: GrantFiled: June 30, 2010Date of Patent: July 30, 2013Assignee: International Business Machines CorporationInventors: Mathew Accapadi, Grover C Davidson, II, Dirk Michel, Bret R Olszewski
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Patent number: 8102246Abstract: A power reset module may reset an automatic shut-off module of a target device by momentarily disrupting power to the automatic shut-off module at a determined interval and automatically restoring power after a time period of up to two minutes. In multiple embodiments, the power reset module comprises an activation switch with an activation switch output coupled to a frequency module. The frequency module may output a frequency module signal on a determined interval via a frequency module output coupled with a reset module. The reset module momentarily transitions a reset switch to a reset state periodically at the determined interval for up to two minutes prior to automatically transitioning the reset switch to a non-reset state.Type: GrantFiled: January 2, 2009Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventor: Grover C. Davidson, II
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Publication number: 20120005448Abstract: Management of a UNIX-style storage pools is enhanced by specially managing one or more memory management inodes associated with pinned and allocated pages of data storage by providing indirect access to the pinned and allocated pages by one or more user processes via a handle, while preventing direct access of the pinned and allocated pages by the user processes without use of the handles; scanning periodically hardware status bits in the inodes to determine which of the pinned and allocated pages have been recently accessed within a pre-determined period of time; requesting via a callback communication to each user process to determine which of the least-recently accessed pinned and allocated pages can be either deallocated or defragmented and compacted; and responsive to receiving one or more page indicators of pages unpinned by the user processes, compacting or deallocating one or more pages corresponding to the page indicators.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: IBM CORPORATIONInventors: Mathew Accapadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20110246800Abstract: Distributing a thread for running on a physical processor and enabling the physical processor to be switched into a low power snooze state when said running thread is IDLE. However, this switching into said low power state is enabled to be delayed by a delay time from an IDLE dispatch from said running thread; such delay is determined by tracking the rate of the number of said IDLE dispatches per processor clock interval and dynamically varying said delay time wherein the delay time is decreased when said rate of IDLE dispatches increases and the delay time is increased when said rate of IDLE dispatches decreases.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Applicant: International Business Machines CorporationInventors: Mathew Accpadi, Grover C. Davidson, II, Dirk Michel, Bret R. Olszewski
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Publication number: 20100171601Abstract: A power reset module may reset an automatic shut-off module of a target device by momentarily disrupting power to the automatic shut-off module at a determined interval and automatically restoring power after a time period of up to two minutes. In multiple embodiments, the power reset module comprises an activation switch with an activation switch output coupled to a frequency module. The frequency module may output a frequency module signal on a determined interval via a frequency module output coupled with a reset module. The reset module momentarily transitions a reset switch to a reset state periodically at the determined interval for up to two minutes prior to automatically transitioning the reset switch to a non-reset state.Type: ApplicationFiled: January 2, 2009Publication date: July 8, 2010Applicant: International Business Machines CorporationInventor: Grover C. Davidson, II