Abstract: A digital AGC system for burst operation, particularly suited for receiving packets in a wireless local area network. One embodiment includes a log detector that provides a signal strength measure, called the received signal strength indication (RSSI) over a wide dynamic range. The AGC system includes estimating the power in a received signal by averaging the log of the signal power. The Start of Packet detection avoids using the radio receiver's main analog to digital converters to preserve power.

Abstract: A digital AGC system for burst operation, particularly suited for receiving packets in a wireless local area network. One embodiment includes a log detector that provides a signal strength measure, called the received signal strength indication (RSSI) over a wide dynamic range. The AGC system includes estimating the power in a received signal by averaging the log of the signal power. The Start of Packet detection avoids using the radio receiver's main analog to digital converters to preserve power.

Abstract: A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance

Abstract: In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quotient selection circuits. Two carry save adders speculatively compute the possible resulting partial remainders corresponding to each possible value, -1, 0, and +1, of the quotient digit by adding the divisor, not adding anything, and adding the two's complement of the divisor, respectively, thus shortening the critical path of a single SRT iteration producing a single quotient digit. The propagation delays of two carry save adders which speculatively compute the possible resulting partial remainders are masked by a longer delay through quotient selection logic.

Abstract: Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact. The enhanced quotient digit selection logic chooses a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen.

Abstract: In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quotient selection circuits. Two carry save adders speculatively compute the possible resulting partial remainders corresponding to each possible value, -1, 0 , and +1, of the quotient digit by adding the divisor, not adding anything, and adding the two's complement of the divisor, respectively, thus shortening the critical path of a single SRT iteration producing a single quotient digit. The propagation delays of two carry save adders which speculatively compute the possible resulting partial remainders are masked by a longer delay through quotient selection logic.

Abstract: A floating point mantissa final addition and rounding unit uses a conditional sum adder to reduce a redundant carry-save format 106-bit mantissa to a non-redundant properly rounded 53-bit double-precision mantissa. The conditional sum adder simultaneously speculatively computes both the sum and the incremented sum of the upper 52 bits of the carry-save portions. A rounding unit speculatively computes the lower one bit and two bits of the mantissa for the cases of mantissa overflow or non-overflow, respectively. The rounding unit produces an overflow carry signal and a non-overflow carry signal. A multiplexor selects the proper 53 mantissa output bits from among the two conditional sum adder outputs and the rounding unit mantissa outputs depending upon the most significant bits of the two conditional sum adder outputs and the overflow and non-overflow carry signals.

Abstract: The same hardware is used to implement calculations of the exponents for multiplication, division, and square root in either double or single precision. A multiplexor selects the appropriate bias value necessary for exponent computation for the given instruction type, operand precision, and output precision. A first operand multiplexor selects either the exponent of the first operand in the case of a multiplication or division instruction, and selects zero in the case of a square root instruction, since the square root operation only requires one operand. The second operand multiplexor selects the second exponent in the case of a multiplication instruction, the one's complement of the second exponent in the case of a division instruction, and the second exponent divided by two during a square root operation. Flip-flop registers latch the exponent and incremented exponent when a division or square root operation is pending.

Abstract: A method for fully supporting floating point multiplication using a combination of partial hardware support and partial software support traps to software when a subnormal operand is encountered and gross underflow cannot be determined without determining the leading zeros in the subnormal mantissa. A simplified hardware multiplier does not require leading zero detection or left or right shifting. The partial hardware support circuit allows single and double precision operands. The hardware multiplier unit only partially supports subnormal operands. If one of the operands is subnormal, the hardware multiplier unit will output zero and a gross underflow signal if the multiplication would result in gross underflow. There is a small minority of operand permutations that are not supported in hardware and thus require a greater time to compute by resorting to software. However, the vast majority of operand permutations gain reduced latency.

Abstract: A rounding circuit for a binary tree floating point multiplier including apparatus for providing the upper bits of a mantissa presuming that no carry-in has occurred without waiting for the generation of a carry-in from lower order bits, apparatus for providing the upper bits of a mantissa presuming that a carry-in has occurred without waiting for the generation of a carry-in from lower order bits; apparatus for providing a first set of lower order bits for the mantissa based on an actual carry-in from a lower order bit adder and a rounding condition, the first set of lower order bits for the mantissa being chose for no mantissa overflow; apparatus for providing a second set of lower order bits for the mantissa based on an actual carry-in from a lower order bit adder and a rounding condition, the second set of lower order bits for the mantissa being chosen for mantissa overflow; and apparatus for selecting upper order bits and lower order bits for the mantissa based on whether a carry-in propagates past the l

Abstract: A binary integer multiplier including a plurality of adder stages, each of such adder stages including a plurality of cells equal to a number of bits in an operand, each of such adder stage including a pair of full adders capable of receiving six input bits and producing two result bits at the significance level of the cell and two carry bits at the next higher significance level, apparatus interconnecting the bits indicating partial products to the input terminals of a cell at each significance level, apparatus interconnecting the carry output terminals of a cell to input terminals of the cell at the next significance level, apparatus interconnecting one carry output terminal of a cell to any unused input terminal at a cell of a particular stage at which only three input signals are provided, and apparatus interconnecting the result terminals of each cell to the input terminals of the cell at the same significance level at the next adder level.