Patents by Inventor Grzegorz J. Pakulski

Grzegorz J. Pakulski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6829275
    Abstract: A semiconductor device such as a buried heterostructure semiconductor laser includes a semiconductor substrate supporting an active region comprised of a multiple quantum well active region and confinement layers having defined gratings and grating overgrowth regions to produce a laser device. The device also includes a current confinement layer including a sequence of doped n-p-n-p semiconductor layers to produce a n-p-n-p blocking structure and a semi-insulating semiconductor material deposited over the n-p-n-p blocking structure.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: December 7, 2004
    Assignee: Bookham Technology, plc
    Inventors: Grzegorz J. Pakulski, D. Gordon Knight, Cornelis Blaauw
  • Publication number: 20040013143
    Abstract: A laser device having an improved electrical confinement has been disclosed The confinement of laser is composed of a material of AlInAs doped with oxygen. Also, it may further comprise aluminum oxide (Al2O3), which may take the form of an aluminum oxide (Al2O3) layer formed along the interface between the confinement and neighboring components of the device.
    Type: Application
    Filed: December 14, 2001
    Publication date: January 22, 2004
    Inventors: Anthony J. Springthorpe, Paul J. Paddon, Grzegorz J. Pakulski
  • Publication number: 20030119222
    Abstract: A semiconductor device such as a buried heterostructure semiconductor laser includes a semiconductor substrate supporting an active region comprised of a multiple quantum well active region and confinement layers having defined gratings and grating overgrowth regions to produce a laser device. The device also includes a current confinement layer including a sequence of doped n-p-n-p semiconductor layers to produce a n-p-n-p blocking structure and a semi-insulating semiconductor material deposited over the n-p-n-p blocking structure.
    Type: Application
    Filed: December 20, 2001
    Publication date: June 26, 2003
    Inventors: Grzegorz J. Pakulski, D. Gordon Knight, Cornelis Blaauw
  • Patent number: 6551936
    Abstract: An improved method for etching a pattern in a semiconductor material is based on the formation of an InP grating mask on the semiconductor material. The formation of the InP grating mask involves the formation of a multi-layered structure on the semiconductor material with an etch-stop layer between two InP layers. A photoresist grating mask corresponding to the pattern to be etched in the semiconductor material is then formed on the top InP layer. Subsequently, a non-selective etch is used to penetrate the top InP layer, the etch-stop layer, and the lower InP layer. A suitable stripping solvent is then used to remove the photoresist followed by a selective etch to clear the remaining exposed InP material, remove contaminated material and to expose the underlying semiconductor material in accordance with the pattern to be etched. Additional masking beyond the InP mask is, therefore, not required.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: April 22, 2003
    Assignee: Bookham Technology plc
    Inventors: Grzegorz J. Pakulski, Richard J. Finlay
  • Publication number: 20020086550
    Abstract: An improved method for etching a pattern in a semiconductor material is based on the formation of an InP grating mask on the semiconductor material. The formation of the InP grating mask involves the formation of a multi-layered structure on the semiconductor material with an etch-stop layer between two InP layers. A photoresist grating mask corresponding to the pattern to be etched in the semiconductor material is then formed on the top InP layer. Subsequently, a non-selective etch is used to penetrate the top InP layer, the etch-stop layer, and the lower InP layer. A suitable stripping solvent is then used to remove the photoresist followed by a selective etch to clear the remaining exposed InP material, remove contaminated material and to expose the underlying semiconductor material in accordance with the pattern to be etched. Additional masking beyond the InP mask is, therefore, not required.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Grzegorz J. Pakulski, Richard J. Finlay