Patents by Inventor Grzegorz Jereczek
Grzegorz Jereczek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11483313Abstract: Technologies for updating an access control list (ACL) table while minimizing disruption includes a network device. The network device receives a request to store a rule in the ACL. The rule is associated with a precedence group. A precedence group is indicative of a placement priority of a given rule in the ACL. The network device determines, as a function of the precedence group, a placement for the requested rule in the ACL. The network device stores the rule according to the determined placement in the ACL.Type: GrantFiled: June 28, 2018Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Real Valiquette, Carl Geoffrion, Andre Sylvain, Grzegorz Jereczek
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Patent number: 11469915Abstract: Technologies include a network switch configured to perform packet replication. The network switch includes a network communicator, an entity manager, and a tag manager. The network communicator is to receive a data packet, and the entity manger is to identify an entity associated with the data packet and determine a tag associated with the entity. Additionally, the tag manager is to determine a packet replication configuration associated with the tag, and perform one or more per-port forwarding actions based on the packet replication configuration. The packet replication configuration includes one or more destination ports to be masked and a number of copies to be replicated to be sent out on of at least one destination port.Type: GrantFiled: June 12, 2018Date of Patent: October 11, 2022Assignee: Intel CorporationInventors: Grzegorz Jereczek, Amruth Gouda Parameshwarappa, Christopher Edmiston, Maciej Andrzej Koprowski
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Publication number: 20220321478Abstract: Examples described herein relate to a switch comprising: circuitry to detect congestion at a target port and re-direct one or more packets directed to the target port to one or more other ports for re-circulation via one or more uncongested ports based on congestion at the target port. In some examples, the circuitry is to identify the target port in the re-directed one or more packets. In some examples, the circuitry is to transmit a congestion level indicator to the one or more other ports based on a congestion level of the target port.Type: ApplicationFiled: June 13, 2022Publication date: October 6, 2022Inventors: Anil VASUDEVAN, Grzegorz JERECZEK, Parthasarathy SARANGAM
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Publication number: 20220311711Abstract: Examples described herein relate to a network interface device that includes circuitry to: adjust a rate of packet transmissions by Explicit Congestion Notification (ECN)-based congestion control based on phase of operation and congestion metrics comprising queue depth at one or more intermediate switches. In some examples, the circuitry is to adjust the rate of packet transmissions by multiplicative decrease or increase based on a number of inflight bytes. In some examples, the circuitry is to adjust the rate of packet transmissions by additive decrease or increase based on congestion metric from the one or more intermediate switches at one or more intermediate switches.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Theodore JEPSEN, Junggun LEE, Grzegorz JERECZEK, Simon WASS
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Publication number: 20220166698Abstract: Examples described herein relate to a packet processing device that includes circuitry to: request network resource consumption data from one or more other packet processing devices by indication in a header of a reliable transport protocol and transmit the request in a packet that includes the indication in the header. In some examples, the header includes an option field of a transmission control protocol (TCP) packet. In some examples, the network resource consumption data includes a largest network resource consumption data in a path from a sender to a receiver, and potentially one or more next largest network resource consumption data.Type: ApplicationFiled: February 8, 2022Publication date: May 26, 2022Inventors: Junggun LEE, Grzegorz JERECZEK, Junho SUH, Anil VASUDEVAN
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Publication number: 20210320866Abstract: Examples described herein relate to a switch that is to receive a message identifying congestion in a second switch; drop the message; generate a pause frame; and cause transmission of the pause frame to at least one sender of packets to a congested queue in the second switch. In some examples, the message includes one or more of: a destination IP address, Differentiated Services Code Point (DSCP) value, or pause duration for the congested queue. In some examples, the DSCP value is to identify a traffic class of the congested queue. In some examples, the pause frame is consistent with Priority Flow Control (PFC) of IEEE 802.1Qbb (2011). In some examples, the switch is to: store, from the message identifying congestion in the second switch, congestion information associated with the congested queue comprising one or more of: destination internet protocol (IP) address, Differentiated Services Code Point (DSCP) value, or pause end time of the congested queue.Type: ApplicationFiled: June 25, 2021Publication date: October 14, 2021Inventors: Yanfang LE, Junggun LEE, Jeremias BLENDIN, Grzegorz JERECZEK, Georgios NIKOLAIDIS
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Patent number: 11025745Abstract: Technologies for end-to-end quality of service for I/O operations include a compute device in an I/O path. The compute device receives from another of the compute devices in the I/O path, an I/O request packet. The I/O request packet includes one or more QoS deadline metadata. The QoS deadline metadata is indicative of latency information relating to a currently executing workload relative to a specified QoS. The compute device evaluates the QoS deadline metadata and assigns a priority to the I/O request packet as a function of the evaluated metadata.Type: GrantFiled: June 28, 2018Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: Piotr Wysocki, Maciej Andrzej Koprowski, Grzegorz Jereczek
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Publication number: 20200412563Abstract: Technologies for sharing packet replication resources include a network switch. The network switch includes a network communicator, an entity manager, and a tag manager. The network communicator is to receive a data packet, and the entity manger is to identify an entity associated with the data packet and determine a tag associated with the entity. Additionally, the tag manager is to determine a packet replication configuration associated with the tag, and perform one or more per-port forwarding actions based on the packet replication configuration. The packet replication configuration includes one or more destination ports to be masked and a number of copies to be replicated to be sent out on each destination port.Type: ApplicationFiled: June 12, 2018Publication date: December 31, 2020Inventors: Grzegorz JERECZEK, Amruth Gouda PARAMESHWARAPPA, Christopher EDMISTON, Maciej Andrzej KOPROWSKI
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Patent number: 10715437Abstract: Examples may include an apparatus having a packet receiver to receive a packet, the packet including a packet header having a deadline and a destination network node. The apparatus includes a routing table including a current latency for a path to the destination network node for the packet. The apparatus further includes a reprioritization component to get the deadline for delivery of the packet to the destination network node, to set a remaining time for the packet to the deadline minus a current time, to subtract the current latency from the remaining time when the packet is to be routed, and to assign the packet to one of a plurality of deadline bins based at least in part on the remaining time, each deadline bin associated with one of a plurality of transmit queues, the plurality of deadline bins arranged in a deadline priority order from a highest priority to a lowest priority.Type: GrantFiled: July 27, 2018Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Grzegorz Jereczek, Maciej Andrzej Koprowski, Piotr Wysocki
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Patent number: 10691506Abstract: Systems and methods for managing locks in a data acquisition system with a distributed data storage are disclosed. In embodiments, a storage node of a data acquisition system with a plurality of storage nodes receives a request for an unprocessed event, where portions of the event data are stored across the plurality of storage nodes. One node of the plurality of nodes holds the lock value for the event. The node receiving the request searches for an event where it stores the lock value that is unlocked. If none is found, the node receiving the request forwards the request to a second node, which repeats the search.Type: GrantFiled: December 28, 2018Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Grzegorz Jereczek, Jakub Radtke, Pawel Makowski, Maciej Maciejewski, Pawel Lebioda, Piotr Pelplinski, Aleksandra Wisz
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Patent number: 10552319Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.Type: GrantFiled: June 1, 2018Date of Patent: February 4, 2020Assignee: Intel CorporationInventors: Grzegorz Jereczek, Pawel Lebioda, Maciej Maciejewski, Pawel Makowski, Piotr Pelplinski, Jakub Radtke, Aleksandra Wisz
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Publication number: 20200007546Abstract: Technologies for updating an access control list (ACL) table while minimizing disruption includes a network device. The network device receives a request to store a rule in the ACL. The rule is associated with a precedence group. A precedence group is indicative of a placement priority of a given rule in the ACL. The network device determines, as a function of the precedence group, a placement for the requested rule in the ACL. The network device stores the rule according to the determined placement in the ACL.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Real Valiquette, Carl Geoffrion, Andre Sylvain, Grzegorz Jereczek
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Publication number: 20190138368Abstract: Systems and methods for managing locks in a data acquisition system with a distributed data storage are disclosed. In embodiments, a storage node of a data acquisition system with a plurality of storage nodes receives a request for an unprocessed event, where portions of the event data are stored across the plurality of storage nodes. One node of the plurality of nodes holds the lock value for the event. The node receiving the request searches for an event where it stores the lock value that is unlocked. If none is found, the node receiving the request forwards the request to a second node, which repeats the search.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Grzegorz JERECZEK, Jakub RADTKE, Pawel MAKOWSKI, Maciej MACIEJEWSKI, Pawel LEBIODA, Piotr PELPLINSKI, Aleksandra WISZ
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Publication number: 20190042443Abstract: Examples may include techniques to manage data in a data acquisition system including allocating memory in a first stage buffer; storing data received by a data provider into the allocated memory in the first stage buffer; and storing a key identifying the stored data and an address in the first stage buffer for the stored data in an entry in a first keys data structure. Further steps include receiving a request from a filtering unit to get the stored data from the first stage buffer, the request including the key; retrieving the address in the first stage buffer from the entry in the first keys data structure associated with the key; and returning the address in the first stage buffer to the filtering unit.Type: ApplicationFiled: March 2, 2018Publication date: February 7, 2019Inventors: Maciej MACIEJEWSKI, Piotr PELPINSKI, Grzegorz JERECZEK, Jakub RADTKE, Wojciech MALIKOWSKI, Pawel MAKOWSKI
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Publication number: 20190042409Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 1, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Grzegorz Jereczek, Pawel Lebioda, Maciej Maciejewski, Pawel Makowski, Piotr Pelplinski, Jakub Radtke, Aleksandra Wisz
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Publication number: 20190044857Abstract: Examples may include an apparatus having a packet receiver to receive a packet, the packet including a packet header having a deadline and a destination network node. The apparatus includes a routing table including a current latency for a path to the destination network node for the packet. The apparatus further includes a reprioritization component to get the deadline for delivery of the packet to the destination network node, to set a remaining time for the packet to the deadline minus a current time, to subtract the current latency from the remaining time when the packet is to be routed, and to assign the packet to one of a plurality of deadline bins based at least in part on the remaining time, each deadline bin associated with one of a plurality of transmit queues, the plurality of deadline bins arranged in a deadline priority order from a highest priority to a lowest priority.Type: ApplicationFiled: July 27, 2018Publication date: February 7, 2019Inventors: Grzegorz JERECZEK, Maciej Andrzej KOPROWSKI, Piotr WYSOCKI
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Publication number: 20190045028Abstract: Technologies for end-to-end quality of service for I/O operations include a compute device in an I/O path. The compute device receives from another of the compute devices in the I/O path, an I/O request packet. The I/O request packet includes one or more QoS deadline metadata. The QoS deadline metadata is indicative of latency information relating to a currently executing workload relative to a specified QoS. The compute device evaluates the QoS deadline metadata and assigns a priority to the I/O request packet as a function of the evaluated metadata.Type: ApplicationFiled: June 28, 2018Publication date: February 7, 2019Inventors: Piotr Wysocki, Maciej Andrzej Koprowski, Grzegorz Jereczek