Patents by Inventor Grzegorz Mrugalski
Grzegorz Mrugalski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11815555Abstract: A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.Type: GrantFiled: September 6, 2019Date of Patent: November 14, 2023Assignee: Siemens Industry Software Inc.Inventors: Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer, Bartosz Wlodarczak
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Patent number: 11585853Abstract: A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.Type: GrantFiled: November 17, 2020Date of Patent: February 21, 2023Assignee: Siemens Industry Software Inc.Inventors: Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
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Publication number: 20220308110Abstract: A circuit comprises scan gating devices inserted between outputs of scan chains and inputs of a test response compactor. The scan gating devices divides the scan chains into groups of scan chains. Each of the scan gating devices operates in either an enabled mode or a disenabled mode based on a first signal. A scan gating device operating in the enabled mode blocks, blocks only at some clock cycles, or does not block a portion of a test response of a test pattern captured by and outputted from a scan chain in the associated scan chain group based on a second signal. Scan gating devices operating in the disenabled mode do not block, or based on a third signal, either block or do not block, a portion of the test response captured by and outputted from all scan chains in each of the associated scan chain groups.Type: ApplicationFiled: September 6, 2019Publication date: September 29, 2022Inventors: Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer, Bartosz Wlodarczak
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Patent number: 11423202Abstract: This application discloses a computing system implementing an automatic test pattern generation tool to perform scan chain diagnosis-driven compaction setting. The computing system can perform fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains. The computing system can determine locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains, and generate a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.Type: GrantFiled: August 31, 2020Date of Patent: August 23, 2022Assignee: Siemens Industry Software Inc.Inventors: Grzegorz Mrugalski, Szczepan Urban, Jakub Janicki
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Publication number: 20220065932Abstract: This application discloses a computing system implementing an automatic test pattern generation tool to perform scan chain diagnosis-driven compaction setting. The computing system can perform fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains. The computing system can determine locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains, and generate a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Inventors: Grzegorz Mrugalski, Szczepan Urban, Jakub Janicki
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Publication number: 20210156918Abstract: A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.Type: ApplicationFiled: November 17, 2020Publication date: May 27, 2021Inventors: Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
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Patent number: 10955460Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.Type: GrantFiled: March 16, 2011Date of Patent: March 23, 2021Assignee: Mentor Graphics CorporationInventors: Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
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Patent number: 10379161Abstract: Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are generated based on combinational paths between scan cells. Scan cells may be assigned to one or more pairs of scan cell partitions based on combinational paths between the scan cells. Each pair of the scan cell partitions comprises one stimuli partition and one compacting partition. Using the plurality of scan cell partitions generated, scan chains are formed based on at least information of combinational paths between scan cell partitions in the plurality of scan cell partitions. The formed scan chains are to be dynamically divided into three groups during a test, which are configured to operate in a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, respectively.Type: GrantFiled: June 17, 2013Date of Patent: August 13, 2019Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
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Patent number: 10120024Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: GrantFiled: October 2, 2017Date of Patent: November 6, 2018Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
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Patent number: 10120029Abstract: Aspects of the disclosed technology relate to low power testing. A low power test circuit comprises a test stimulus source, a controller; and a grouping and selection unit. The grouping and selection unit has inputs coupled to the test stimulus source and the controller and has outputs coupled to a plurality of scan chains. The grouping and selection unit is configured to dynamically group scan chains in the plurality of scan chains into a plurality of scan chain groups and to selectively output either original test pattern values generated by the test stimulus source or a constant value to each scan chain group in the plurality of scan chain groups based on control signals received from the controller.Type: GrantFiled: May 12, 2015Date of Patent: November 6, 2018Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Sylwester Milewski, Grzegorz Mrugalski, Jerzy Tyszer
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Publication number: 20180156867Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: ApplicationFiled: October 2, 2017Publication date: June 7, 2018Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
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Publication number: 20180143249Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: ApplicationFiled: January 19, 2018Publication date: May 24, 2018Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee
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Patent number: 9933485Abstract: Various aspects of the disclosed technology relate to deterministic built-in self-test. A deterministic built-in self-test system comprises: a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and a controller configured at least to output a control signal that inverts outputs of the decompressor at one or more scan shift clock cycles based on control data stored on chip, enabling the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.Type: GrantFiled: February 23, 2016Date of Patent: April 3, 2018Assignee: Mentor Graphics CorporationInventors: Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer
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Patent number: 9874606Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: GrantFiled: June 21, 2016Date of Patent: January 23, 2018Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee
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Patent number: 9778316Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: GrantFiled: February 1, 2016Date of Patent: October 3, 2017Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
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Patent number: 9714981Abstract: Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli.Type: GrantFiled: May 9, 2016Date of Patent: July 25, 2017Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
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Publication number: 20170052227Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: ApplicationFiled: June 21, 2016Publication date: February 23, 2017Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee
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Publication number: 20160320450Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: ApplicationFiled: February 1, 2016Publication date: November 3, 2016Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
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Publication number: 20160252573Abstract: Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli.Type: ApplicationFiled: May 9, 2016Publication date: September 1, 2016Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
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Publication number: 20160245863Abstract: Various aspects of the disclosed technology relate to deterministic built-in self-test. A deterministic built-in self-test system comprises: a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and a controller configured at least to output a control signal that inverts outputs of the decompressor at one or more scan shift clock cycles based on control data stored on chip, enabling the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.Type: ApplicationFiled: February 23, 2016Publication date: August 25, 2016Inventors: Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer