Abstract: A wafer scale system-in-package structure and a method for forming the same, are provided. The package structure includes: a silicon substrate comprising an upper surface and a lower surface opposite to the upper surface; functional submodules mounted on the upper surface of the silicon substrate and arranged in an array, wherein each of the functional submodules comprises four corners and four edges each between adjacent corners, and the functional submodules are electrically connected to the silicon substrate; a first bridge structure mounted on the upper surface of the silicon substrate at the edges of the functional submodules; a second bridge structure mounted on the upper surface of the silicon substrate at the corners of the functional submodules; and a first molding layer located on the upper surface of the silicon substrate and covering the functional submodules.