Patents by Inventor Gu-Huan Li
Gu-Huan Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160240233Abstract: A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node. The switch unit is responsive to a first control signal and a second control signal, and is configured to connect the first memory cell to the true node and to disconnect the second memory cell from the complement node in response to the first control signal and to connect the second memory cell to the complement node and to disconnect the first memory cell from the true node in response to the second control signal. A semiconductor device that includes the memory is also disclosed. A method for testing the memory is also disclosed.Type: ApplicationFiled: February 13, 2015Publication date: August 18, 2016Inventors: CHENG-HSIUNG KUO, GU-HUAN LI, JIH-CHEN WANG, CHUNG-CHIEH CHEN
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Publication number: 20160211030Abstract: A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.Type: ApplicationFiled: January 20, 2015Publication date: July 21, 2016Inventors: HSU-SHUN CHEN, GU-HUAN LI, CHENG-HSIUNG KUO, YUE-DER CHIH
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Publication number: 20160209854Abstract: A circuit for generating an output voltage and method for setting an output voltage of a low dropout regulator are provided. A current source is configured to generate a reference current, and an error amplifier has a first input, a second input, and a single-ended output. The first input is connected to a reference voltage, and the second input is connected to an output node of the circuit via a feedback resistor. A pass transistor includes a control electrode connected to the single-ended output of the error amplifier, a first electrode connected to a power supply voltage, and a second electrode connected to the output node of the circuit. A first branch of a current mirror is connected to the current source, and a second branch of the current mirror is connected to the second terminal of the feedback resistor. The output node provides an output voltage of the circuit.Type: ApplicationFiled: January 20, 2015Publication date: July 21, 2016Inventors: CHEN-LUN YEN, GU-HUAN LI, CHUNG-CHIEH CHEN, CHENG-HSIUNG KUO
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Patent number: 9324383Abstract: An integrated circuit that includes a generator unit connected to one or more pull-up units, one or more pull-up units connected to one or more source lines and an array of memory cells connected to the one or more source lines. The generator unit is configured to set a first voltage signal of each pull-up unit of the one or more pull-up units. Each pull-up unit of the one or more pull-up units is connected with the corresponding source line of the one or more source lines and is configured to set a current of the corresponding source line of the one or more source lines. The array of memory cells is electrically connected to the one or more source lines and one or more bit lines.Type: GrantFiled: March 20, 2014Date of Patent: April 26, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Gu-Huan Li, Hsu-Shun Chen, Chung-Chieh Chen, Cheng-Hsiung Kuo
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Publication number: 20160035398Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix.Type: ApplicationFiled: October 13, 2015Publication date: February 4, 2016Inventors: Yue-Der CHIH, Cheng-Hsiung KUO, Gu-Huan LI, Chien-Yin LIU
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Patent number: 9208847Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.Type: GrantFiled: October 30, 2013Date of Patent: December 8, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der Chih, Cheng-Hsiung Kuo, Gu-Huan Li, Chien-Yin Liu
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Patent number: 9190995Abstract: An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.Type: GrantFiled: November 19, 2014Date of Patent: November 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jerry Chen, Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Publication number: 20150269974Abstract: An integrated circuit that includes a generator unit connected to one or more pull-up units, one or more pull-up units connected to one or more source lines and an array of memory cells connected to the one or more source lines. The generator unit is configured to set a first voltage signal of each pull-up unit of the one or more pull-up units. Each pull-up unit of the one or more pull-up units is connected with the corresponding source line of the one or more source lines and is configured to set a current of the corresponding source line of the one or more source lines. The array of memory cells is electrically connected to the one or more source lines and one or more bit lines.Type: ApplicationFiled: March 20, 2014Publication date: September 24, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Gu-Huan LI, Hsu-Shun CHEN, Chung-Chieh CHEN, Cheng-Hsiung KUO
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Publication number: 20150221383Abstract: A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.Type: ApplicationFiled: January 31, 2014Publication date: August 6, 2015Inventors: Hsu-Shun Chen, Cheng-Hsiung Kuo, Gu-Huan Li, Chung-Chieh Chen, Yue-Der Chih
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Publication number: 20150131372Abstract: A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yue-Der CHIH, Cheng-Hsiung KUO, Gu-Huan LI
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Publication number: 20150117131Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.Type: ApplicationFiled: October 30, 2013Publication date: April 30, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yue-Der CHIH, Cheng-Hsiung KUO, Gu-Huan LI, Chien-Yin LIU
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Publication number: 20150070057Abstract: An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.Type: ApplicationFiled: November 19, 2014Publication date: March 12, 2015Inventors: Jerry Chen, Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Patent number: 8928372Abstract: An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.Type: GrantFiled: March 8, 2013Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jerry Chen, Hsu-Shun Chen, Gu-Huan Li, Cheng-Hsiung Kuo, Yue-Der Chih
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Patent number: 8629706Abstract: A power switch includes a control circuit, a cross-coupled amplifier, a first switching circuit coupled between a first output terminal and the first controlled ground terminal, and a second switching circuit coupled between a second output terminal and the second controlled ground terminal. The control circuit is configured to connect the second controlled ground terminal to a ground during a first period that a voltage level at the first output terminal is switched from the ground to a first voltage level and to set the second controlled ground terminal at an elevated ground level during a second period that the voltage level at the first output terminal remains at the first voltage level.Type: GrantFiled: October 13, 2011Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsu-Shun Chen, Cheng-Hsiung Kuo, Gu-Huan Li, Yue-Der Chih
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Publication number: 20130093499Abstract: A power switch includes a control circuit, a cross-coupled amplifier, a first switching circuit coupled between a first output terminal and the first controlled ground terminal, and a second switching circuit coupled between a second output terminal and the second controlled ground terminal. The control circuit is configured to connect the second controlled ground terminal to a ground during a first period that a voltage level at the first output terminal is switched from the ground to a first voltage level and to set the second controlled ground terminal at an elevated ground level during a second period that the voltage level at the first output terminal remains at the first voltage level.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsu-Shun CHEN, Cheng-Hsiung KUO, Gu-Huan LI, Yue-Der CHIH
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Patent number: 8294450Abstract: An integrated circuit structure includes a bandgap reference circuit and a start-up circuit. The bandgap reference circuit includes a positive power supply node and a PMOS transistor including a source coupled to the positive power supply node. The start-up circuit is configured to be turned on during a start-up stage of the bandgap reference circuit, and to be turned off after the start-up stage. The start-up circuit includes a switch configured to interconnect a gate and a drain of the PMOS transistor during the start-up stage, and to disconnect the gate of the PMOS transistor from the drain of the PMOS transistor after the start-up stage.Type: GrantFiled: December 28, 2009Date of Patent: October 23, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Gu-Huan Li
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Patent number: 8068356Abstract: This invention discloses a voltage boost circuit which comprise at least one capacitor with a first terminal connected to an output of the voltage boost circuit, a controllable switch connected between a second terminal of the capacitor and a voltage source, the second terminal being different from the first terminal, and a voltage level detector detecting the output voltage level of the voltage boost circuit and providing a control signal to the controllable switch, wherein when the output voltage exceeds a predetermined level the controllable switch is off, and when the output voltage is lower than the predetermined level the controllable switch is on.Type: GrantFiled: November 20, 2008Date of Patent: November 29, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Gu-Huan Li
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Publication number: 20110025291Abstract: An integrated circuit structure includes a bandgap reference circuit and a start-up circuit. The bandgap reference circuit includes a positive power supply node and a PMOS transistor including a source coupled to the positive power supply node. The start-up circuit is configured to be turned on during a start-up stage of the bandgap reference circuit, and to be turned off after the start-up stage. The start-up circuit includes a switch configured to interconnect a gate and a drain of the PMOS transistor during the start-up stage, and to disconnect the gate of the PMOS transistor from the drain of the PMOS transistor after the start-up stage.Type: ApplicationFiled: December 28, 2009Publication date: February 3, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Gu-Huan Li
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Publication number: 20090295354Abstract: This invention discloses a voltage boost circuit which comprise at least one capacitor with a first terminal connected to an output of the voltage boost circuit, a controllable switch connected between a second terminal of the capacitor and a voltage source, the second terminal being different from the first terminal, and a voltage level detector detecting the output voltage level of the voltage boost circuit and providing a control signal to the controllable switch, wherein when the output voltage exceeds a predetermined level the controllable switch is off, and when the output voltage is lower than the predetermined level the controllable switch is on.Type: ApplicationFiled: November 20, 2008Publication date: December 3, 2009Inventor: Gu-Huan Li