Patents by Inventor Guan Cheng Chen
Guan Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990471Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.Type: GrantFiled: August 10, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
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Publication number: 20240162227Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.Type: ApplicationFiled: November 19, 2023Publication date: May 16, 2024Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG, Kuan-Lun CHENG
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Patent number: 11984488Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.Type: GrantFiled: April 30, 2021Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng
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Publication number: 20240154043Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.Type: ApplicationFiled: January 2, 2024Publication date: May 9, 2024Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240145540Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.Type: ApplicationFiled: January 20, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Guan-Lin CHEN, Jung-Chien CHENG, Chih-Hao WANG
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Patent number: 11942513Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.Type: GrantFiled: January 10, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Jui-Chien Huang
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Patent number: 11942478Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.Type: GrantFiled: May 6, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Guan-Lin Chen
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Publication number: 20240096895Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
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Publication number: 20240097051Abstract: A Schottky diode includes a substrate, a first drift region in the substrate, a second drift region in the substrate, a first dielectric layer disposed over the substrate, a first doped region in the first drift region, a second doped region in the second drift region, a third doped region in the first drift region, and a metal field plate disposed over the first dielectric layer. The first drift region and the first doped region include a first conductivity type. The second drift region, the second doped region and third doped region include a second conductivity type complementary to the first conductivity type. The first dielectric layer overlaps a portion of the first drift region and a portion of the second drift region. The second doped region is separated from the first doped region.Type: ApplicationFiled: January 16, 2023Publication date: March 21, 2024Inventors: GUAN-YI LI, CHIA-CHENG HO, CHAN-YU HUNG, FEI-YUN CHEN
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Patent number: 10628449Abstract: A system, method and computer program product configured for processing database data in a distributed database system, wherein the distributed database system comprises a plurality of computing nodes communicatively coupled via computer networks, the method comprising: creating a plurality of different data replicas wherein each of the data replicas is created in the following way: sorting the database data according to at least one data attribute; generating a row key based on the at least one data attribute; and using the sorted database data with the row key as the data replica, storing different data replicas in different computing nodes; and creating an index for each of the data replicas according to its row key.Type: GrantFiled: October 12, 2018Date of Patent: April 21, 2020Assignee: International Business Machines CorporationInventors: Guan Cheng Chen, Ju Wei Shi, Kun Wang, Ben Bo Yang, Jia Zou
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Publication number: 20190050470Abstract: A system, method and computer program product configured for processing database data in a distributed database system, wherein the distributed database system comprises a plurality of computing nodes communicatively coupled via computer networks, the method comprising: creating a plurality of different data replicas wherein each of the data replicas is created in the following way: sorting the database data according to at least one data attribute; generating a row key based on the at least one data attribute; and using the sorted database data with the row key as the data replica, storing different data replicas in different computing nodes; and creating an index for each of the data replicas according to its row key.Type: ApplicationFiled: October 12, 2018Publication date: February 14, 2019Inventors: Guan Cheng Chen, Ju Wei Shi, Kun Wang, Ben Bo Yang, Jia Zou
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Patent number: 10140351Abstract: A computer program product configured to implement a method for processing database data in a distributed database system, wherein the distributed database system comprises a plurality of computing nodes communicatively coupled via computer networks, the method comprising: creating a plurality of different data replicas wherein each of the data replicas is created in the following way: sorting the database data according to at least one data attribute; generating a row key based on the at least one data attribute; and using the sorted database data with the row key as the data replica, storing different data replicas in different computing nodes; and creating an index for each of the data replicas according to its row key.Type: GrantFiled: July 6, 2016Date of Patent: November 27, 2018Assignee: International Business Machines CorporationInventors: Guan Cheng Chen, Ju Wei Shi, Kun Wang, Ben Bo Yang, Jia Zou
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Patent number: 10083066Abstract: A computer implemented method and system for data processing. An example method includes setting at least one SMT preliminary value for at least one operating node; monitoring performance metrics for the at least one operating node set to the at least one SMT preliminary value; and determining a SMT revised value based on performance metrics. An example system includes a memory; a processor communicatively coupled to the memory; and a feature selection module communicatively coupled to the memory and processor. The feature selection module performs a method that includes setting, using a setting device, at least one SMT preliminary value for at least one operating node; monitoring, using a monitoring device, performance metrics for the at least one operating node set to the at least one SMT preliminary value; and determining, using a determining device, a SMT revised value based on performance metrics.Type: GrantFiled: May 28, 2014Date of Patent: September 25, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guan Cheng Chen, Qi Guo, Jian Li, Xin Li, Yan Li
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Patent number: 9870270Abstract: A method and device for realizing graph processing based on the MapReduce architecture is disclosed in the invention. The method includes the steps of: receiving an input file of a graph processing job; predicting a MapReduce task execution time distribution of the graph processing job using an obtained MapReduce task degree-execution time relationship distribution and a degree distribution of the graph processing job; and dividing the input file of the graph processing job into input data splits of MapReduce tasks according to the predicted MapReduce task execution time distribution of the graph processing job.Type: GrantFiled: December 19, 2016Date of Patent: January 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guan Cheng Chen, Ju Wei Shi, Liu Tao, Chen Wang, Kun Wang
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Patent number: 9663865Abstract: The disclosure provides a catalyst structure for electrolysis of water. The catalyst structure includes a ferric oxide support and a plurality of cobalt-containing compound catalysts. The plurality of cobalt-containing compound catalysts attach to a surface of the ferric oxide support. The disclosure also provides a method of forming a catalyst structure for electrolysis of water.Type: GrantFiled: January 5, 2016Date of Patent: May 30, 2017Assignee: National Taiwan University of Science and TechnologyInventors: Chen-Hao Wang, Guan-Cheng Chen, Kai-Chin Wang
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Publication number: 20170097853Abstract: A method and device for realizing graph processing based on the MapReduce architecture is disclosed in the invention. The method includes the steps of: receiving an input file of a graph processing job; predicting a MapReduce task execution time distribution of the graph processing job using an obtained MapReduce task degree-execution time relationship distribution and a degree distribution of the graph processing job; and dividing the input file of the graph processing job into input data splits of MapReduce tasks according to the predicted MapReduce task execution time distribution of the graph processing job.Type: ApplicationFiled: December 19, 2016Publication date: April 6, 2017Inventors: Guan Cheng Chen, Ju Wei Shi, Liu Tao, Chen Wang, Kun Wang
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Publication number: 20170051418Abstract: The disclosure provides a catalyst structure for electrolysis of water. The catalyst structure includes a ferric oxide support and a plurality of cobalt-containing compound catalysts. The plurality of cobalt-containing compound catalysts attach to a surface of the ferric oxide support. The disclosure also provides a method of forming a catalyst structure for electrolysis of water.Type: ApplicationFiled: January 5, 2016Publication date: February 23, 2017Inventors: Chen-Hao WANG, Guan-Cheng CHEN, Kai-Chin WANG
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Patent number: 9569457Abstract: A data processing method for a distributed system, the distributed system comprising a master storage node and multiple slave storage nodes, includes: storing, responsive to a request for writing a data file, multiple replications of the data file on the multiple slave storage nodes, each of the replications being segmented into data blocks of a same size, wherein the sizes of the segmented data blocks of at least two replications are different; and storing distribution information of the multiple replications.Type: GrantFiled: October 14, 2013Date of Patent: February 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guan Cheng Chen, Jian Li, Xin Li, Yan Li, Qiming Teng
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Patent number: 9558045Abstract: A method and device for realizing graph processing based on the MapReduce architecture is disclosed in the invention. The method includes the steps of: receiving an input file of a graph processing job; predicting a MapReduce task execution time distribution of the graph processing job using an obtained MapReduce task degree-execution time relationship distribution and a degree distribution of the graph processing job; and dividing the input file of the graph processing job into input data splits of MapReduce tasks according to the predicted MapReduce task execution time distribution of the graph processing job.Type: GrantFiled: January 30, 2014Date of Patent: January 31, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guan Cheng Chen, Ju Wei Shi, Liu Tao, Chen Wang, Kun Wang
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Publication number: 20160314178Abstract: A computer program product configured to implement a method for processing database data in a distributed database system, wherein the distributed database system comprises a plurality of computing nodes communicatively coupled via computer networks, the method comprising: creating a plurality of different data replicas wherein each of the data replicas is created in the following way: sorting the database data according to at least one data attribute; generating a row key based on the at least one data attribute; and using the sorted database data with the row key as the data replica, storing different data replicas in different computing nodes; and creating an index for each of the data replicas according to its row key.Type: ApplicationFiled: July 6, 2016Publication date: October 27, 2016Inventors: Guan Cheng Chen, Ju Wei Shi, Kun Wang, Ben Bo Yang, Jia Zou