Patents by Inventor Guan-Lin Pan

Guan-Lin Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250125216
    Abstract: The present disclosure provides a die. The die of the present disclosure has a top surface, a plurality of side surfaces, a bottom surface, a circuit layer and a platform. The bottom surface is connected to the side surfaces. The circuit layer is formed on the bottom surface. The platform is disposed around the top surface and is parallel to the top surface and the bottom surface. The distance from the platform to the bottom surface is less than that from the top surface to the bottom surface. The platform is perpendicularly connected to the side surfaces. The present disclosure further provides a method of manufacturing the above die and a semiconductor package with the die.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 17, 2025
    Inventors: YUEH-MING TUNG, CHIA-MING YANG, GUAN-LIN PAN, YING-CHIH LEE, PO-YEN YEN
  • Publication number: 20250062281
    Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a first die, a plurality of first bonding pads, a plurality of first conductive bumps, a molding layer and a redistribution layer. The first die has a top surface and a bottom surface opposing to the top surface. The first bonding pads are disposed on the top surface of the first die. The first conductive bumps are disposed on the first bonding pads, and the first conductive bumps are electrically connected with the first die. The molding layer covers the top surface of the first die and exposes the first conductive bumps. The redistribution layer is disposed on the molding layer to electrically connect to the first conductive bumps. The present disclosure further provides a method of manufacturing the above semiconductor package.
    Type: Application
    Filed: March 15, 2024
    Publication date: February 20, 2025
    Inventors: Yueh-Ming Tung, Chia-Ming Yang, Tsun-Lung Hsieh, Guan-Lin Pan, Po-Yen Yen
  • Patent number: 11462454
    Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: October 4, 2022
    Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITED
    Inventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan
  • Publication number: 20220285217
    Abstract: The wafer thinning method of the present disclosure includes: providing a wafer having a front surface and a back surface opposite to the front surface; grinding the back surface of the wafer with a grinding bit to thin the wafer to a predetermined thickness; dicing the wafer with a dicing blade; ablating the wafer by performing a chemical solution or plasma process on the back surface of the wafer to thin the wafer; and separating the wafer into a plurality of dies.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 8, 2022
    Inventors: YUEH-MING TUNG, CHIA-MING YANG, GUAN-LIN PAN, JUNG-WEI CHEN, JIAN-DE LEU
  • Publication number: 20220199428
    Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.
    Type: Application
    Filed: February 2, 2021
    Publication date: June 23, 2022
    Inventors: YUEH-MING TUNG, CHIA-MING YANG, JUNG-WEI CHEN, JIAN-DE LEU, GUAN-LIN PAN
  • Publication number: 20220189842
    Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.
    Type: Application
    Filed: January 26, 2021
    Publication date: June 16, 2022
    Inventors: YUEH-MING TUNG, CHIA-MING YANG, JUNG-WEI CHEN, JIAN-DE LEU, GUAN-LIN PAN
  • Patent number: 11355356
    Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: June 7, 2022
    Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITED
    Inventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan