Abstract: A vertical gate nonvolatile NAND array includes a plurality of vertically stacked NAND strings of nonvolatile memory cells, a plurality of word lines arranged orthogonally over the plurality of vertically stacked NAND strings, and a plurality of vertical columns of conductive gate material electrically coupled to the plurality of word lines. The plurality of vertically stacked NAND strings are with vertically stacked semiconductor strips having opposite sides including a first side and a second side. The vertical columns in the plurality of vertical columns are gates to only one side of the first side and the second side of the opposite sides of the vertically stacked semiconductor strips. The vertical columns in the plurality of vertical columns are gates to adjacent stacks in the plurality of vertically stacked NAND strings.

Abstract: A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active layers. An isolation material is formed over the lining, over and in between the spaced-apart stacks. A plurality of trenches in the isolation material is arranged to cross over the plurality of spaced-apart stacks of active strips, leaving at least a residue of the lining on a bottom of the trenches between the stacks of active strips and over a sidewall of the spaced-apart stacks of active strips. The residue of the lining on the bottom of the trenches and the sidewalls of the spaced-apart stacks of active layers is selectively removed. Then the plurality of trenches is filled with conductive or semiconductor material to form the damascene structure.

Abstract: A vertical gate nonvolatile NAND array includes a plurality of vertically stacked NAND strings of nonvolatile memory cells, a plurality of word lines arranged orthogonally over the plurality of vertically stacked NAND strings, and a plurality of vertical columns of conductive gate material electrically coupled to the plurality of word lines. The plurality of vertically stacked NAND strings are with vertically stacked semiconductor strips having opposite sides including a first side and a second side. The vertical columns in the plurality of vertical columns are gates to only one side of the first side and the second side of the opposite sides of the vertically stacked semiconductor strips. The vertical columns in the plurality of vertical columns are gates to adjacent stacks in the plurality of vertically stacked NAND strings.

Abstract: A 3D memory device includes a first plurality and a second plurality of stacks of semiconductor material strips on a substrate. The second plurality of stacks of gate material strips on the substrate is interleaved with, and coplanar with, the first plurality of stacks. The second plurality of stacks is configured as gates for the first plurality of stacks. A first plurality of word lines is arranged orthogonally over, and having surfaces conformal with, the first plurality of stacks, such that a 3D array of memory elements is established at cross-points between surfaces of the first plurality of stacks and the plurality of word lines.

Abstract: A 3D memory device includes a first plurality and a second plurality of stacks of semiconductor material strips on a substrate. The second plurality of stacks of gate material strips on the substrate is interleaved with, and coplanar with, the first plurality of stacks. The second plurality of stacks is configured as gates for the first plurality of stacks. A first plurality of word lines is arranged orthogonally over, and having surfaces conformal with, the first plurality of stacks, such that a 3D array of memory elements is established at cross-points between surfaces of the first plurality of stacks and the plurality of word lines.

Abstract: For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The second semiconductor layer is formed over the first semiconductor layer and includes a recess in a vertical direction towards the first semiconductor layer. The third semiconductor layer is formed in the recess of the second semiconductor layer and includes a seam or void in the recess.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The second semiconductor layer is formed over the first semiconductor layer and includes a recess in a vertical direction towards the first semiconductor layer. The third semiconductor layer is formed in the recess of the second semiconductor layer and includes a seam or void in the recess.

Abstract: For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material.

Abstract: A method of forming a conductor structure can result in vertical sidewalls. The method deposits a lining over a plurality of spaced-apart stacks of active layers. An isolation material is formed over the lining, over and in between the spaced-apart stacks. A plurality of trenches in the isolation material is arranged to cross over the plurality of spaced-apart stacks of active strips, leaving at least a residue of the lining on a bottom of the trenches between the stacks of active strips and over a sidewall of the spaced-apart stacks of active strips. The residue of the lining on the bottom of the trenches and the sidewalls of the spaced-apart stacks of active layers is selectively removed. Then the plurality of trenches is filled with conductive or semiconductor material to form the damascene structure.

Abstract: A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers.

Abstract: A method is provided for use with an IC device including a stack including a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending from a connector surface to respective conductive layers. The method forms landing areas on the plurality of conductive layers in the stack. The landing areas are without overlying conductive layers in the stack. The method forms etch stop layers over corresponding landing areas. The etch stop layers have thicknesses that correlate with depths of the corresponding landing areas. The method fills over the landing areas and the etch stop layers with a dielectric fill material. Using a patterned etching process, the method forms a plurality of vias extending through the dielectric fill material and the etch stop layers to the landing areas in the plurality of conductive layers.

Abstract: The switch transistors in the NAND strings have combinations of threshold voltage levels that vary across the levels of a three dimensional memory array. A bias arrangement is applied to the select lines electrically coupled to the switch transistors. The NAND strings on a particular level of a three dimensional memory array are selected. The NAND strings on other levels are deselected.

Abstract: The switch transistors in the NAND strings have combinations of threshold voltage levels that vary across the levels of a three dimensional memory array. A bias arrangement is applied to the select lines electrically coupled to the switch transistors. The NAND strings on a particular level of a three dimensional memory array are selected. The NAND strings on other levels are deselected.