Patents by Inventor Guan-Shyan Lin

Guan-Shyan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of adjusting signal to noise ratio of SRAM and invertor structure
    Patent number: 10504788
    Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.
    Type: Grant
    Filed: March 10, 2019
    Date of Patent: December 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chi Lee, Han-Tsun Wang, Chang-Hung Chen, Po-Yu Yang, Mei-Ying Fan, Mu-Kai Tsai, Guan-Shyan Lin, Tsz-Hui Kuo, Cheng-Hsiung Chen
  • METHOD OF ADJUSTING SIGNAL TO NOISE RATIO OF SRAM AND INVERTOR STRUCTURE
    Publication number: 20190318964
    Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.
    Type: Application
    Filed: March 10, 2019
    Publication date: October 17, 2019
    Inventors: Wei-Chi Lee, Han-Tsun Wang, Chang-Hung Chen, Po-Yu Yang, Mei-Ying Fan, Mu-Kai Tsai, Guan-Shyan Lin, Tsz-Hui Kuo, Cheng-Hsiung Chen
  • Method of adjusting signal to noise ratio of SRAM and invertor structure
    Patent number: 10276446
    Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. A gate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chi Lee, Han-Tsun Wang, Chang-Hung Chen, Po-Yu Yang, Mei-Ying Fan, Mu-Kai Tsai, Guan-Shyan Lin, Tsz-Hui Kuo, Cheng-Hsiung Chen