Abstract: Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

Abstract: Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

Abstract: Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

Abstract: Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entity, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.

Abstract: Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

Abstract: Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entity, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.

Abstract: Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entity, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.