Abstract: In a computer device, a memory sharing control device is deployed between a processor and a memory pool, and the processor accesses the memory pool via the memory sharing control device. Different processing units, such as processors or cores in processors, access one memory in the memory pool in different time periods, so that the memory is shared by a plurality of processing units, and utilization of memory resources is improved.

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Abstract: In an NVMe-based storage system, a host is connected to an NVMe controller through a PCIe bus, and the NVMe controller is connected to a storage medium. The NVMe controller receives from the host a data packet that carries payload data and an association identifier. The association identifier associates the payload data with a write instruction. The NVMe controller obtains the write instruction according to the association identifier, and then writes the payload data into the storage medium according to the write instruction.

Abstract: A non-volatile memory express (NVMe)-based data read method, apparatus, and system are provided. In various embodiments, a read instruction can be triggered by a host. The read instruction carries indication information of a first address opened by the host to an NVMe controller for addressing and accessing. In those embodiments, the host after obtaining the read instruction can send a data packet to the host. The data packet carries the first address and payload data. Still in those embodiments, the host can, after receiving the data packet, determine a second address based on the first address, and store the payload data into storage space indicated by the second address. The second address may be a private memory address of the host. Because a relationship between the second address and a communication protocol is broken, and the host may access the second address without being restricted by the communication protocol.

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Abstract: In an NVMe-based storage system, a host is connected to an NVMe controller through a PCIe bus, and the NVMe controller is connected to a storage medium. The NVMe controller receives from the host a data packet that carries payload data and an association identifier. The association identifier associates the payload data with a write instruction. The NVMe controller obtains the write instruction according to the association identifier, and then writes the payload data into the storage medium according to the write instruction.

Abstract: A non-volatile memory express (NVMe)-based data read method, apparatus, and system are provided. In various embodiments, a read instruction can be triggered by a host. The read instruction carries indication information of a first address opened by the host to an NVMe controller for addressing and accessing. In those embodiments, the host after obtaining the read instruction can send a data packet to the host. The data packet carries the first address and payload data. Still in those embodiments, the host can, after receiving the data packet, determine a second address based on the first address, and store the payload data into storage space indicated by the second address. The second address may be a private memory address of the host. Because a relationship between the second address and a communication protocol is broken, and the host may access the second address without being restricted by the communication protocol.

Abstract: A flash medium access method, including selecting, by a controller, a target function queue from N function queues according to a predefined rule, where the target function queue is a non-empty queue, a flash medium in which a die associated with the target function queue is located is in an idle state, obtaining a basic instruction from the target function queue, determining, according to preset queue mapping information, the die associated with the target function queue, where the controller is connected to at least one flash medium, and the queue mapping information indicates that the N function queues are in a one-to-one mapping relationship with the N dies, generating, according to a preset signal generation rule, a time sequence signal corresponding to the basic instruction, and sending the time sequence signal to the flash medium in which the associated die is located.

Abstract: A flash device access method, apparatus, and system, where a flash device includes a controller and a storage array. The method includes dividing the storage array into a specific storage unit and a user storage unit, such that a storage feature of the specific storage unit is the same as that of the user storage unit, writing, by the controller, specific data into the specific storage unit, reading, by the controller, the specific data stored in the specific storage unit, determining, by the controller, a decision voltage (Vread) based on the read specific data, and reading, by the controller using the determined Vread, the user data stored in the user storage unit. Hence, incorrect determining of the data stored in the flash device may be reduced using the access method, apparatus, and system.

Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Abstract: A method for managing a solid state disk (SSD) storage device and accessing data of the SSD storage device in order to resolve problems of highly complex data management in an SDD and different service lives of NAND flash physical pages in a NAND flash physical block where, lengths of a user data area, primary metadata, and an error checking and correction (ECC) code in each storage unit of an SSD storage device are set to fixed values. As a result, a format of data stored in the storage unit is fixed, and the ECC code can also ensure consistency between data in the user data area and the primary metadata at a fixed code rate in order to ensure correctness and integrity of the data in the user data area and the primary metadata.

Abstract: A flash medium access method, including selecting, by a controller, a target function queue from N function queues according to a predefined rule, where the target function queue is a non-empty queue, a flash medium in which a die associated with the target function queue is located is in an idle state, obtaining a basic instruction from the target function queue, determining, according to preset queue mapping information, the die associated with the target function queue, where the controller is connected to at least one flash medium, and the queue mapping information indicates that the N function queues are in a one-to-one mapping relationship with the N dies, generating, according to a preset signal generation rule, a time sequence signal corresponding to the basic instruction, and sending the time sequence signal to the flash medium in which the associated die is located.

Abstract: A flash device access method, apparatus, and system, where a flash device includes a controller and a storage array. The method includes dividing the storage array into a specific storage unit and a user storage unit, such that a storage feature of the specific storage unit is the same as that of the user storage unit, writing, by the controller, specific data into the specific storage unit, reading, by the controller, the specific data stored in the specific storage unit, determining, by the controller, a decision voltage (Vread) based on the read specific data, and reading, by the controller using the determined Vread, the user data stored in the user storage unit. Hence, incorrect determining of the data stored in the flash device may be reduced using the access method, apparatus, and system.

Abstract: A hot swappable device includes a port, a firmware module, and an interrupt masking module. The port includes a Peripheral Component Interface express Physical Layer, and the Peripheral Component Interface express Physical Layer includes multiple lanes lanes. The Peripheral Component Interface express Physical Layer detects an analog signal in each of the multiple lanes, when it is detected that an amplitude of an analog signal in one of the multiple lanes is less than a preset threshold, generates an ALOS signal corresponding to the lane, and transmits the ALOS signal to the interrupt masking module. The interrupt masking module generates an ALOS interrupt signal corresponding to the lane and sends the ALOS interrupt signal to the firmware module. If the firmware module receives, in a preset time period, an ALOS interrupt signal corresponding to each lane, the firmware module resets the port.

Abstract: A method for managing a solid state disk (SSD) storage device and accessing data of the SSD storage device in order to resolve problems of highly complex data management in an SDD and different service lives of NAND flash physical pages in a NAND flash physical block where, lengths of a user data area, primary metadata, and an error checking and correction (ECC) code in each storage unit of an SSD storage device are set to fixed values. As a result, a format of data stored in the storage unit is fixed, and the ECC code can also ensure consistency between data in the user data area and the primary metadata at a fixed code rate in order to ensure correctness and integrity of the data in the user data area and the primary metadata.

Abstract: A hot swappable device includes a port, a firmware module, and an interrupt masking module. The port includes a Peripheral Component Interface express Physical Layer, and the Peripheral Component Interface express Physical Layer includes multiple lanes lanes. The Peripheral Component Interface express Physical Layer detects an analog signal in each of the multiple lanes, when it is detected that an amplitude of an analog signal in one of the multiple lanes is less than a preset threshold, generates an ALOS signal corresponding to the lane, and transmits the ALOS signal to the interrupt masking module. The interrupt masking module generates an ALOS interrupt signal corresponding to the lane and sends the ALOS interrupt signal to the firmware module. If the firmware module receives, in a preset time period, an ALOS interrupt signal corresponding to each lane, the firmware module resets the port.