Abstract: Disclosed are an instruction execution method and apparatus for graph computation. The method includes the following steps: S1: sending operators of each node in a computational graph used for neural network computation to an operator interpreter; S2: building, by the operator interpreter, instructions in operation; S3: defining an instruction dependency relationship; S4: building an instruction dependency relationship graph; S5: building a topological order of parallel instructions; S6: scheduling the parallel instructions to hardware resources; S7: building shortest schedules for the parallel instructions: the shortest time required to execute the parallel instructions under the condition of limited hardware resources; and S8: releasing the completed instructions.

Abstract: A glass fiber filter element for visible light photocatalysis and air purification and a method for preparing the same. The glass fiber filter element includes 4 to 7 wt % of nanoparticles including at least one selected from zinc oxide, graphene oxide, titanium oxide, and reduced graphene oxide, 2 to 7 wt % of silver nanowires, 3 to 12 wt % of an adhesive system, and 78 to 91 wt % of a glass fiber mat, based on the total weight of the glass fiber filter element. The glass fiber mat is made of at least two glass fibers with different diameters, and the diameters are in a range of 0.15 to 3.5 ?m. The nanoparticles have a particle size from 1 to 200 nm, and the silver nanowires have a diameter of 15 to 50 nm.

Abstract: A memory optimization method includes: compiling a neural network into a computational graph for neural network computation on a computer; transforming the computational graph into a topological graph; constructing a life cycle relationship graph of tensor variables in the computational graph; and analyzing a life cycle relationship among tensor variables in a node of the computational graph; iteratively merging those tensor variables connected by lines of the second type and caching into a memory any tensor variable that goes beyond a number of idle registers and is not allocated to a register, until all tensor variables that go beyond the number of the idle registers and are not allocated to registers are cached into the memory; caching any node of the life cycle relationship graph with a degree smaller than a number of registers into a stack.

Abstract: The present disclosure discloses a method for execution of a computational graph in a neural network model and an apparatus thereof, including: creating task execution bodies on a native machine according to a physical computational graph compiled and generated by a deep learning framework, and designing a solution for allocating a plurality of idle memory blocks to each task execution body, so that the entire computational graph participates in deep learning training tasks of different batches of data in a pipelining and parallelizing manner.

Abstract: A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

Abstract: Provided is a closed cooking cavity (100) formed by means of a shell in a sealed manner; a working space for accommodating main cooking equipment is formed in an interior of the cooking cavity (100), the shell is provided with communicating openings which are corresponding to the main cooking equipment and adapted for communicating the interior and exterior of the cooking cavity (100), and accessory cooking equipment arranged at the exterior of the cooking cavity (100) is connected with corresponding main cooking equipment arranged in the interior of the cooking cavity through corresponding communicating openings so as to achieve corresponding cooking functions. A closed cooking system comprises the cooking cavity (100) and a cooking machine comprises the closed cooking system.

Abstract: A viewing angle widening film, a manufacturing method thereof, and a display device are provided. A first film layer of the viewing angle widening film includes protrusions spaced apart from each other and extended along a first direction. The protrusions include a first protrusion and a second protrusion arranged on a side of the first protrusion away from a flat layer, a surface of the second protrusion on a side away from the flat layer is an arc surface, and a diffusion effect of the second protrusion is weaker than that of the first protrusion.

Abstract: A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

Abstract: A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

Abstract: A display panel includes a thin film transistor (TFT) array substrate, an opposite substrate, and a liquid crystal layer disposed between the TFT array substrate and the opposite substrate. The TFT array substrate includes a first substrate. The opposite substrate includes a second substrate. The display panel further includes a first viewing-angle improving layer disposed between the first substrate and the second substrate. The first viewing-angle improving layer adjoins one film layer on the first substrate or the second substrate. The first viewing-angle improving layer is disposed between the first substrate and the second substrate so that the first viewing-angle improving layer can be a stacked part manufactured integratedly with other film layers of the display panel. Thus, manufacture of the first viewing-angle improving layer can overcome a size limitation of a mold in a nanoimprinting technology, effectively improving a large-viewing-angle-display effect of a large-size display panel.

Abstract: Sensing methods and systems for transformers, and the construction thereof, are described herein. Example transformer systems and example methods for constructing a core for the system are disclosed. The example system includes a core with a bottom plate, two or more limbs mounted to the bottom plate and a top plate enclosing the core. At least one of the bottom plate, the limbs and the top plate is formed with a sensing component therein. The sensing component can be mounted to a spacer layer assembled within a stack of laminated layers. The sensing component can be mounted within a path defined within the spacer layer, for example. Methods for detecting operating conditions within the transformer are also disclosed.

Abstract: An apparatus includes a junction termination edge, a unipolar power transistor, and an RC snubber. The RC snubber has a capacitor between a poly silicon structure and a semiconductor substrate, and part of the junction termination edge. The capacitor has a p-n junction. The RC snubber has a poly silicon resistor between a source of the unipolar power transistor and a first layer forming the capacitor. The unipolar transistor and the RC snubber are coupled in parallel. The RC snubber and the unipolar power transistor are formed monolithically on the semiconductor substrate.

Abstract: A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

Abstract: A single chip power semiconductor device includes: first and second load terminals; a semiconductor body integrated in the single chip and coupled to the load terminals and configured to conduct a load current along a load current path between the load terminals; a control terminal and at least one control electrode electrically connected thereto, the at least one control electrode being electrically insulated from the semiconductor body and configured to control the load current based on a control voltage between the control terminal and the first load terminal; a protection structure integrated, separately from the load current path, in the single chip and including a series connection of pn junctions with first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type. The series connection of the pn-junctions is connected in forward bias between the control terminal and the first load terminal.

Abstract: A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

Abstract: A viewing angle expansion film, a method for preparing the same, and a display device are provided. The viewing angle expansion film includes a first film layer having a flat layer, a plurality of first projections, and a plurality of second projections, and a second film layer disposed on the first film layer. The plurality of first projections and the plurality of second projections are arrayed on the flat layer. The second film layer is filled in gaps between the first projections and the second projections adjacent to the first projections, gaps between adjacent first projections, and gap between adjacent second projections. A refractive index of the second film layer is greater than a refractive index of the first film layer.

Abstract: An image-based lighting effect processing method and apparatus, and a device, and a storage medium are provided. The method includes: obtaining an image, a lighting effect material picture, and a first position of a simulated light source in a three-dimensional space, wherein the lighting effect material picture comprises lighting information; according to an object image in the image, generating a first three-dimensional mesh model of an object on the surface of the object image; determining lighting information of a point on the first three-dimensional mesh model according to the first position of the simulated light source, a distance between the point on the first three-dimensional mesh model and the surface of the image, and the lighting effect material picture; and rendering the object image in the image according to the lighting information of the point on the first three-dimensional mesh model to obtain a first lighting effect rendered picture.

Abstract: Sensing methods and systems for transformers, and the construction thereof, are described herein. Example transformer systems and example methods for constructing a core for the system are disclosed. The example system includes a core with a bottom plate, two or more limbs mounted to the bottom plate and a top plate enclosing the core. At least one of the bottom plate, the limbs and the top plate is formed with a sensing component therein. The sensing component can be mounted to a spacer layer assembled within a stack of laminated layers. The sensing component can be mounted within a path defined within the spacer layer, for example. Methods for detecting operating conditions within the transformer are also disclosed.

Abstract: A semiconductor device includes a transistor cell with a source region of a first conductivity type and a gate electrode. The source region is formed in a wide bandgap semiconductor portion. A diode chain includes a plurality of diode structures. The diode structures are formed in the wide bandgap semiconductor portion and electrically connected in series. Each diode structure includes a cathode region of the first conductivity type and an anode region of a complementary second conductivity type. A gate metallization is electrically connected with the gate electrode and with a first one of the anode regions in the diode chain. A source electrode structure is electrically connected with the source region and with a last one of the cathode regions in the diode chain.