Patents by Inventor Guang-Bo Gao
Guang-Bo Gao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10128228Abstract: A semiconductor device includes a type IV semiconductor base substrate, a first type III-V semiconductor layer formed over the base substrate, a second type III-V semiconductor layer formed over the first type III-V semiconductor layer. A two-dimensional charge carrier gas forms at an interface between the first and second type III-V semiconductor layers. First and second electrically conductive device terminals are in ohmic contact with the two-dimensional charge carrier gas. A gate electrode is formed on the first type III-V semiconductor layer and is configured to control a conduction state of the two-dimensional charge carrier gas. An electrically insulating region is disposed over the second type III-V semiconductor layer and is laterally between the gate electrode and the second electrically conductive device terminal. At least one diode is formed on the electrically insulating region and is electrically connected between the gate electrode and the second electrically conductive device terminal.Type: GrantFiled: June 22, 2017Date of Patent: November 13, 2018Assignee: Infineon Technologies Americas Corp.Inventors: Guang-Bo Gao, Zhaofeng Wang
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Patent number: 6689677Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.Type: GrantFiled: November 1, 2002Date of Patent: February 10, 2004Assignee: STMicroelectronics, Inc.Inventors: Guang-Bo Gao, Hoang Huy Hoang
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Patent number: 6563143Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.Type: GrantFiled: July 29, 1999Date of Patent: May 13, 2003Assignee: STMicroelectronics, Inc.Inventors: Guang-Bo Gao, Hoang Huy Hoang
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Publication number: 20030068849Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.Type: ApplicationFiled: November 1, 2002Publication date: April 10, 2003Inventors: Guang-Bo Gao, Hoang Huy Hoang
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Patent number: 6531351Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.Type: GrantFiled: October 3, 2001Date of Patent: March 11, 2003Assignee: STMicroelectronics, Inc.Inventors: Guang-Bo Gao, Hoang Huy Hoang
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Publication number: 20020125476Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.Type: ApplicationFiled: October 3, 2001Publication date: September 12, 2002Inventors: Guang-Bo Gao, Hoang Huy Hoang
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Publication number: 20020024094Abstract: A GaAs/Ge on Si CMOS integrated circuit is formed to improve transistor switching (propagation) delay by taking advantage of the high electron mobility for GaAs in the N-channel device and the high hole mobility for Ge in the P-channel device. A semi-insulating (undoped) layer of GaAs is formed over a silicon base to provide a buffer layer eliminating the possibility of latch-up. GaAs and Ge wells are then formed over the semi-insulating GaAs layer, electrically isolated by standard thermal oxide and/or flowable oxide (HSQ). N-channel MOS devices and P-channel MOS devices are formed in the GaAs and Ge wells, respectively, and interconnected to form the integrated circuit. Gate electrodes for devices in both wells may be polysilicon, while the gate oxide is preferably gallium oxide for the N-channel devices and silicon dioxide for the P-channel devices. Minimum device feature sizes may be 0.5 &mgr;m to avoid hot carrier degradation while still achieving performance increases over 0.Type: ApplicationFiled: July 29, 1999Publication date: February 28, 2002Inventors: GUANG-BO GAO, HOANG HUY HOANG