Patents by Inventor GuangNing Li

GuangNing Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230418725
    Abstract: The innovation disclosed and claimed herein, in one aspect thereof, comprises systems and methods of reviewing submitted programming solutions in response to a requested task. The innovation receives a solution for a task that is part of a project. The innovation analyzes the solution and the user according to a set of predetermined rules. The innovation determines a set of predetermined rules based on an analysis of previously received solutions. The innovation determines similarities between the received solution to previously received solutions. The innovation determines a subset of previously received solutions that are most similar to the received solution. The innovation analyzes the subset of previously received solutions, including a history of each solution in the subset. The innovation determines a likelihood of faults in the received solution based on the analysis of the subset.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 28, 2023
    Inventors: Nathan Charles Freeling, Catherine Guangning Li, Iain Thomas Raleigh
  • Patent number: 10600700
    Abstract: This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: March 24, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: YiPing Mao, GuangNing Li
  • Publication number: 20190074232
    Abstract: This application relates to the field of semiconductor technologies, and discloses a test structure and a manufacturing method therefor. Forms of the method may include: providing a top wafer structure, where the top wafer structure includes a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer; providing a bottom wafer structure, where the bottom wafer structure includes a bottom wafer and multiple second pads that are spaced from each other at a top of the bottom wafer, where a side surface of at least one of two adjacent second pads has an insulation layer; bonding the multiple first pads with the multiple second pads in a eutectic bonding manner, where each first pad is bonded with a second pad, to form multiple pads. This application may mitigate a problem that bonded pads are connected to each other.
    Type: Application
    Filed: June 1, 2018
    Publication date: March 7, 2019
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: YiPing Mao, GuangNing Li