Abstract: A successive approximation analog-to-digital converter includes a first capacitance bank, a second capacitance bank, a bridge capacitor, a switch set, a comparator and a successive approximation register logic circuit. The first capacitance bank is connected with a first node. The second capacitance bank is connected with a second node. The bridge capacitor is connected between the first node and the second node. Two first input terminals of the comparator are connected with the first node and the intermediate level, respectively. An output terminal of the comparator generates a comparing signal. The successive approximation register logic circuit receives the comparing signal, and generates the switching signal and a digital data signal. The switch set selectively provides one of a low reference level, a high reference level, an input level and an intermediate level to the first capacitance bank and the second capacitance bank.