Patents by Inventor GUANGYAN LUO

GUANGYAN LUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory decoding system
    Patent number: 10176854
    Abstract: A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: January 8, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Guangyan Luo, Hao Ni, Chuntian Yu, Xiaoyan Liu
  • MEMORY DECODING SYSTEM
    Publication number: 20180122437
    Abstract: A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 3, 2018
    Inventors: GUANGYAN LUO, HAO NI, CHUNTIAN YU, XIAOYAN LIU
  • Control method and control apparatus of memory decoding system
    Patent number: 9892769
    Abstract: The present disclosure provides control methods and control apparatus thereof and reference current modules of memory decoding systems. An exemplary control method of a memory decoding system comprising a decoder having at least a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a fourth NMOS transistor, a memory cell, and at least a first bit line and a second bit line, includes applying a first control signal, being at a logic low level during a first read operation stage of a read operation and at a logic high level during a second read operation stage after the first read operation stage of the read operation, to a gate of the first PMOS transistor; applying a second control signal to a gate of the second PMOS transistor; and applying a fourth control signal to a gate of the first NMOS transistor.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: February 13, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Guangyan Luo, Hao Ni, Chuntian Yu, Xiaoyan Liu
  • CONTROL METHOD AND CONTROL APPARATUS OF MEMORY DECODING SYSTEM
    Publication number: 20170062028
    Abstract: The present disclosure provides control methods and control apparatus thereof and reference current modules of memory decoding systems. An exemplary control method of a memory decoding system comprising a decoder having at least a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a fourth NMOS transistor, a memory cell, and at least a first bit line and a second bit line, includes applying a first control signal, being at a logic low level during a first read operation stage of a read operation and at a logic high level during a second read operation stage after the first read operation stage of the read operation, to a gate of the first PMOS transistor; applying a second control signal to a gate of the second PMOS transistor; and applying a fourth control signal to a gate of the first NMOS transistor.
    Type: Application
    Filed: August 29, 2016
    Publication date: March 2, 2017
    Inventors: GUANGYAN LUO, HAO NI, CHUNTIAN YU, XIAOYAN LIU
  • Selected gate driver circuit in memory circuits, and control device and control method thereof
    Patent number: 9583156
    Abstract: A selected gate (SG) driver circuit, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor. A source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: February 28, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Guangyan Luo, Hao Ni, Changwei Yin, Xiao Zheng
  • SELECTED GATE DRIVER CIRCUIT IN MEMORY CIRCUITS, AND CONTROL DEVICE AND CONTROL METHOD THEREOF
    Publication number: 20170004864
    Abstract: The present disclosure provides a selected gate (SG) driver circuit, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor. A source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 5, 2017
    Inventors: GUANGYAN LUO, HAO NI, CHANGWEI YIN, XIAO ZHENG