Patents by Inventor Guang-Yu Lo

Guang-Yu Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230207668
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.
    Type: Application
    Filed: March 6, 2023
    Publication date: June 29, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
  • Publication number: 20230207669
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.
    Type: Application
    Filed: March 7, 2023
    Publication date: June 29, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
  • Patent number: 11631753
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: April 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu
  • Patent number: 11145733
    Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: October 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Yu-Hsiang Lin, Po-Wen Su, Chung-Fu Chang, Guang-Yu Lo, Chun-Tsen Lu
  • Publication number: 20200235227
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.
    Type: Application
    Filed: February 22, 2019
    Publication date: July 23, 2020
    Inventors: Chung-Fu Chang, Kuan-Hung Chen, Guang-Yu Lo, Chun-Chia Chen, Chun-Tsen Lu