Abstract: A random estimation analog-to-digital converter for converting a first analog signal into a digital signal includes a random bit generator, a digital-to-analog converter, a summer, an M-bit analog-to-digital converter, and a digital combiner. The random bit generator generates random least significant bits (LSBs) and the digital-to-analog converter then converts the random LSBs into a second analog signal. The summer subtracts the second analog signal from the first analog signal in the analog domain. The M-bit analog-to-digital converter then converts the modified first analog signal into the most significant bits (MSBs) of the digital image signal. The digital combiner combines the random LSBs with the MSBs in the digital domain to generate the digital signal. In one example, the random LSBs are extra bits that are beyond the maximum resolution of the M-bit analog-to-digital converter.

Abstract: A random estimation analog-to-digital converter for converting a first analog signal into a digital signal includes a random bit generator, a digital-to-analog converter, a summer, an M-bit analog-to-digital converter, and a digital combiner. The random bit generator generates random least significant bits (LSBs) and the digital-to-analog converter then converts the random LSBs into a second analog signal. The summer subtracts the second analog signal from the first analog signal in the analog domain. The M-bit analog-to-digital converter then converts the modified first analog signal into the most significant bits (MSBs) of the digital image signal. The digital combiner combines the random LSBs with the MSBs in the digital domain to generate the digital signal. In one example, the random LSBs are extra bits that are beyond the maximum resolution of the M-bit analog-to-digital converter.

Abstract: A circuit for providing signal amplification with reduced fixed pattern noise. In an embodiment, the circuit includes an amplifier and a plurality of legs coupled in parallel with one another between a first node for an input of the amplifier and a second node for an output of the amplifier. Control logic selects a first combination of the plurality of legs for a first configuration of the circuit to provide a first loop gain with the amplifier. In another embodiment, the control logic further selects a second combination of the plurality of legs for a second configuration of the circuit to provide a second loop gain with the amplifier, wherein the first loop gain is substantially equal to the second loop gain.

Abstract: A comparator circuit for generating a signal representing a comparison of an input signal and a reference signal. In an embodiment, the comparator circuit includes a first stage and a second stage to provide respective signal amplification, where switch circuitry of the second stage switchedly couples respective elements of the first and second stages. The comparator circuit further includes a third stage to generate an output signal based on an intermediate signal of the second stage. In another embodiment, feedback circuitry of the comparator circuit is to selectively control a voltage of the output stage based on the output signal.

Abstract: Embodiments of an image sensor including a pixel array with a plurality of pixels arranged into rows and columns. Control circuitry coupled to the pixels in each row, and an analog-to-digital converter is coupled to the pixels in each column of the pixel array. Each analog-to-digital converter includes a ramp comparator, and a variable current source coupled to the ramp comparator to provide a variable bias current to the ramp comparator. The bias current can adjusted during reading of a row of pixels according to a dynamic bias current profile that maintains at least a specified margin between the random noise of the pixels and an acceptable noise level. Other embodiments are disclosed and claimed.

Abstract: A switch circuit including structures to reduce the effects of charge injection. In an embodiment, a first transistor of the switch circuit is to receive a first signal and first and second dummy transistors of the switch circuit are each to receive a second signal, wherein the first transistor is connected between the first and second dummy transistors. The second signal is complementary to the first signal. In another embodiment, the first transistor, the first dummy transistor and the second dummy transistors are each connected via respective body connections to a first low supply voltage.

Abstract: A method of capturing an image includes activating a first image sensor and capturing a sequence of images with a second image sensor. A determination is made as to whether the sequence of images captured by the second image sensor includes a shutter gesture. If a shutter gesture is included in the sequence of images captured by the second image sensor, the first image sensor captures a target image in response.

Abstract: A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed.

Abstract: A technique for obtaining a corrected pixel value is disclosed. The technique includes measuring a first dark current of a dark calibration pixel of a pixel array and measuring a second dark current of an imaging pixel of the pixel array. A dark current ratio is calculated based on the first dark current and the second dark current. An image charge is acquired with the imaging pixel where the image charge is accumulated over a first time period. A charge is acquired with the dark calibration pixel where the charge is accumulated over a second time period. The second time period is approximately equal to the first time period divided by the dark current ratio. A corrected imaging pixel value is calculated using a first readout from the imaging pixel and a second readout from the dark calibration pixel.

Abstract: An example image sensor includes a plurality of pixels arranged in an array of columns and rows, a row driver, and a control logic circuit. The row driver is coupled to pixels in a row of the array to provide a variable driving voltage to drive transistors included in the pixels of the row. The control logic circuit is coupled to provide one or more control logic signals to the row driver. The row driver adjusts a magnitude of the driving voltage in response to the one or more control logic signals.

Abstract: An imaging sensor having reduced column fixed pattern noise includes a plurality of imaging pixels and a column sampling circuit. The plurality of imaging pixels are arranged in a column the column sampling circuit is coupled to the column. A plurality of sampling channels are included in the column sampling circuit, where the column sampling circuit randomly selects a first sampling channel from among the plurality of sampling channels to sample a first data signal from a pixel included in the plurality of imaging pixels and where the column sampling circuit randomly selects a second sampling channel from among the plurality of sampling channels to sample a second data signal from the pixel.

Abstract: An image sensor includes a plurality of pixel cells organized into rows and columns of a pixel array. A bit line is coupled to each of the pixel cells within a line of the pixel array. Readout circuitry is coupled to the bit line to readout the image data from the pixel cells within the line. The readout circuitry includes a line amplifier coupled to the bit line to amplify the image data and first and second sample and convert circuits coupled in parallel to an output of the line amplifier to reciprocally and contemporaneously sample the image data and convert the image data from analog values to digital values.

Abstract: An imaging sensor having reduced column fixed pattern noise includes a plurality of imaging pixels and a column sampling circuit. The plurality of imaging pixels are arranged in a column the column sampling circuit is coupled to the column. A plurality of sampling channels are included in the column sampling circuit, where the column sampling circuit randomly selects a first sampling channel from among the plurality of sampling channels to sample a first data signal from a pixel included in the plurality of imaging pixels and where the column sampling circuit randomly selects a second sampling channel from among the plurality of sampling channels to sample a second data signal from the pixel.

Abstract: Embodiments of the present invention synthesize a core frequency divider by adding a switching feedback shell and using multiple clock edges to trigger the frequency divider. Feedback logic is used to determine which edge will be used. Embodiments allow multiple recursive use, which boosts the overall speed resulting frequency divider circuit 2N times faster than the core frequency divider.

Abstract: A backside illuminated imaging sensor pixel includes a photodiode region, a pixel circuitry region, and a storage capacitor. The photodiode region is disposed within a semiconductor die for accumulating an image charge. The pixel circuitry region is disposed on the semiconductor die between a frontside of the semiconductor die and the photodiode region. The pixel circuitry region overlaps at least a portion of the photodiode region. The storage capacitor is included within the pixel circuitry region overlapping the photodiode region and is selectively coupled to the photodiode region to temporarily store image charges accumulated thereon.

Abstract: The present invention provides a method, system and apparatus for a time stamped visual motion sensor that provides a compact pixel size, higher speed motion detection and accuracy in velocity computation, high resolution, low power integration and reduces the data transfer and computation load of the following digital processor. The present invention provides a visual motion sensor cell that includes a photosensor, an edge detector connected to the photosensor and a time stamp component connected to the edge detector. The edge detector receives inputs from the photosensor and generates a pulse when a moving edge is detected. The time stamp component tracks a time signal and samples a time voltage when the moving edge is detected. The sampled time voltage can be stored until the sampled time voltage is read. In addition, the edge detector can be connected to one or more neighboring photosensors to improve sensitivity and robustness.