Abstract: Various embodiments described herein provide for a method for reduced power consumption by a memory system. A memory system of some embodiments monitors power state change requests received by the memory system from a host system, and determines a pattern of power state change requests received from the host system. Based on the determined pattern, the memory system can decide to activate or deactivate a reduced power consumption mode on the memory system. A reduced power consumption mode can comprise a first set of operation parameters that cause a memory system to operate with lower power consumption than a second set of operation parameters associated with a current operation mode, where the current operation mode is associated with a current power state set or last requested by the host system.

Abstract: Various embodiments described herein provide for a method for reduced power consumption by a memory system. A memory system of some embodiments monitors power state change requests received by the memory system from a host system, and determines a pattern of power state change requests received from the host system. Based on the determined pattern, the memory system can decide to activate or deactivate a reduced power consumption mode on the memory system. A reduced power consumption mode can comprise a first set of operation parameters that cause a memory system to operate with lower power consumption than a second set of operation parameters associated with a current operation mode, where the current operation mode is associated with a current power state set or last requested by the host system.

Abstract: A program operation is executed on a memory sub-system. In response to receiving a request to execute a read operation, executing a first program suspend operation to suspend the program operation. In response to a completion of the read operation, a program resume operation is executed to resume execution of the program operation. A delay period is established following execution of the program resume operation during which execution of the program operation is completed. A second program suspend operation is executed following the delay period.

Abstract: A program operation is executed on a memory sub-system. In response to receiving a request to execute a read operation, executing a first program suspend operation to suspend the program operation. In response to a completion of the read operation, a program resume operation is executed to resume execution of the program operation. A delay period is established following execution of the program resume operation during which execution of the program operation is completed. A second program suspend operation is executed following the delay period.

Abstract: A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.

Abstract: A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.

Abstract: A Galois field multiplier is provided, comprising a multiplication circuit for inputting two m bits binary multiplicators and outputting their product, wherein m is an integral power of 2, and the output of said multiplication circuit is consisted of a high bits portion output and a low bits portion output; a memory for storing a Galois field multiplication coefficient array calculated from a selected Galois field primitive polynomial; a first module for performing operation on the output of said multiplication circuit and the Galois field multiplication coefficient array stored in said memory to obtain the product of the two m bits binary multiplicators over Galois field. The Galois field multiplier has small hardware footprint, short response latency and strong universality.