Abstract: Various engineered substrate techniques for gallium nitride devices are described that address limitations of conventional substrate approaches. For example, various techniques are described for implementing silicon carbide-on-poly-aluminum nitride (poly-AlN) and sapphire-on-poly-AlN engineered substrates using smart cut processes, hydrogen implantation and exfoliation, and advanced field management approaches to improve device performance while maintaining cost-effectiveness. The engineered substrates described provide the lattice matching and thermal benefits of silicon carbide or sapphire surfaces, for example, while utilizing the CTE matching and cost advantages of poly-AlN handle wafers.

Abstract: Techniques to increase the number of current paths (or “channels”) in a GaN transistor, without increasing the device area, thereby decreasing the on-resistance. In addition, this disclosure describes techniques to utilize back-side field management to improve the device's performance. For example, the techniques can include using p-type implantation into the substrate, e.g., silicon carbide (SiC), as a field management tool to form a superjunction device, thereby increasing the effective field and reducing the on-resistance multiplied by the output charge (Qoss).

Abstract: Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and/or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

Abstract: Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and/or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

Abstract: A semiconductor device including a transistor having a threshold voltage for switching the transistor from a first conductive state to a second conductive state. The transistor includes a first region formed by a first compound semiconductor material and a second region formed by a second compound semiconductor material, where the second region overlying the first region and forming a two-dimensional electron gas (2DEG) at a junction with the first region. The transistor further includes a buried field plate disposed proximate to the first region so that the 2DEG is interposed between the buried field plate and the second region. The semiconductor device further includes a control circuit configured to adjust the threshold voltage of the transistor by providing a bias voltage to the buried field plate responsive to an input signal received at the transistor.

Abstract: Techniques to increase the number of current paths (or “channels”) in a GaN transistor, without increasing the device area, thereby decreasing the on-resistance. In addition, this disclosure describes techniques to utilize back-side field management to improve the device's performance. For example, the techniques can include using p-type implantation into the substrate, e.g., silicon carbide (SiC), as a field management tool to form a superjunction device, thereby increasing the effective field and reducing the on-resistance multiplied by the output charge (Qoss).