Patents by Inventor Guanghui GENG
Guanghui GENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11314675Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.Type: GrantFiled: October 22, 2019Date of Patent: April 26, 2022Assignee: Arm LimitedInventors: Guanghui Geng, Andrew David Tune, Daniel Adam Sara, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal
-
Patent number: 11281403Abstract: Circuitry comprises attribute storage circuitry having a plurality of entries to hold data defining at least a transaction attribute of one or more respective data handling transactions initiated by transaction source circuitry; comparator circuitry to compare a transaction attribute of a given data handling transaction with data held by the attribute storage circuitry to detect whether the given data handling transaction would be resolved by any data handling transaction for which attribute data is held by a respective entry in the attribute storage circuitry; and control circuitry to associate the given data handling transaction with the respective entry in the attribute storage circuitry to form a set of associated data handling transactions when the comparator circuitry detects that the given data handling transaction would be fulfilled by the data handling transaction for which attribute data is held by the respective entry in the attribute storage circuitry; the control circuitry comprising output circuType: GrantFiled: March 26, 2020Date of Patent: March 22, 2022Assignee: Arm LimitedInventors: Thomas Franz Gaertner, Viswanath Chakrala, Guanghui Geng
-
Publication number: 20210303201Abstract: Circuitry comprises attribute storage circuitry having a plurality of entries to hold data defining at least a transaction attribute of one or more respective data handling transactions initiated by transaction source circuitry; comparator circuitry to compare a transaction attribute of a given data handling transaction with data held by the attribute storage circuitry to detect whether the given data handling transaction would be resolved by any data handling transaction for which attribute data is held by a respective entry in the attribute storage circuitry; and control circuitry to associate the given data handling transaction with the respective entry in the attribute storage circuitry to form a set of associated data handling transactions when the comparator circuitry detects that the given data handling transaction would be fulfilled by the data handling transaction for which attribute data is held by the respective entry in the attribute storage circuitry; the control circuitry comprising output circuType: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Inventors: Thomas Franz GAERTNER, Viswanath CHAKRALA, Guanghui GENG
-
Patent number: 10771194Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.Type: GrantFiled: May 25, 2018Date of Patent: September 8, 2020Assignee: ARM LimitedInventors: Andrew David Tune, Guanghui Geng, Zheng Xu
-
Patent number: 10761561Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.Type: GrantFiled: May 25, 2018Date of Patent: September 1, 2020Assignee: Arm LimitedInventors: Saira Samar Malik, David Joseph Hawkins, Andrew David Tune, Guanghui Geng, Julian Jose Hilgemberg Pontes
-
Patent number: 10579469Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.Type: GrantFiled: May 25, 2018Date of Patent: March 3, 2020Assignee: Arm LimitedInventors: Guanghui Geng, Andrew David Tune
-
Publication number: 20200050568Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.Type: ApplicationFiled: October 22, 2019Publication date: February 13, 2020Inventors: Guanghui GENG, Andrew David TUNE, Daniel Adam SARA, Phanindra Kumar MANNAVA, Bruce James MATHEWSON, Jamshed JALAL
-
Publication number: 20190363829Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.Type: ApplicationFiled: May 25, 2018Publication date: November 28, 2019Inventors: Andrew David TUNE, Guanghui GENG, Zheng XU
-
Publication number: 20190361486Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.Type: ApplicationFiled: May 25, 2018Publication date: November 28, 2019Inventors: Saira Samar MALIK, David Joseph HAWKINS, Andrew David TUNE, Guanghui GENG, Julian Jose Hilgemberg PONTES
-
Publication number: 20190361770Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.Type: ApplicationFiled: May 25, 2018Publication date: November 28, 2019Inventors: Guanghui Geng, Andrew David Tune
-
Patent number: 10489323Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.Type: GrantFiled: December 20, 2016Date of Patent: November 26, 2019Assignee: ARM LimitedInventors: Guanghui Geng, Andrew David Tune, Daniel Adam Sara, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal
-
Publication number: 20190266010Abstract: A transaction handling device comprises transaction handling circuitry to handle a transaction request for a data processing transaction, the transaction request having an associated identifier such that at least an aspect of processing for each of a set of transaction requests having the same identifier must be performed in the order of issue of that set of transactions; and detection circuitry to detect the state of an indicator associated with the identifier to indicate whether that identifier relates to more than one concurrently pending transaction request.Type: ApplicationFiled: December 13, 2017Publication date: August 29, 2019Inventors: Andrew David TUNE, Daniel SARA, Guanghui GENG
-
Publication number: 20180173660Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.Type: ApplicationFiled: December 20, 2016Publication date: June 21, 2018Inventors: Guanghui GENG, Andrew David TUNE, Daniel Adam SARA, Phanindra Kumar MANNAVA, Bruce James MATHEWSON, Jamshed JALAL
-
Patent number: 9906440Abstract: Arbitrating and multiplexing circuitry 28 comprises arbitrating tree circuitry having X arbitrating levels and multiplexing tree circuitry having Y multiplexing levels. The Y multiplexing levels comprise a first set of multiplexing levels upstream of a second set of multiplexing levels. The first set of multiplexing levels operate in parallel with at least some of the arbitrating levels. The second set of multiplexing levels operate in series with the X arbitrating levels such that the second set of multiplexing levels completes the required selection to provide the final output following completion of, and in dependence upon, the arbitration by the arbitrating tree circuitry.Type: GrantFiled: June 9, 2015Date of Patent: February 27, 2018Assignee: ARM LimitedInventors: Rakesh Raman, Andrew David Tune, Guanghui Geng
-
Publication number: 20160014050Abstract: Arbitrating and multiplexing circuitry 28 comprises arbitrating tree circuitry having X arbitrating levels and multiplexing tree circuitry having Y multiplexing levels. The Y multiplexing levels comprise a first set of multiplexing levels upstream of a second set of multiplexing levels. The first set of multiplexing levels operate in parallel with at least some of the arbitrating levels. The second set of multiplexing levels operate in series with the X arbitrating levels such that the second set of multiplexing levels completes the required selection to provide the final output following completion of, and in dependence upon, the arbitration by the arbitrating tree circuitry.Type: ApplicationFiled: June 9, 2015Publication date: January 14, 2016Inventors: Rakesh RAMAN, Andrew David TUNE, Guanghui GENG