Patents by Inventor Guangle ZHOU
Guangle ZHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10283567Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.Type: GrantFiled: February 24, 2017Date of Patent: May 7, 2019Assignee: SanDisk Technologies LLCInventors: Juan Saenz, Deepak Kamalanathan, Guangle Zhou, Ming-Che Wu, Tanmay Kumar
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Publication number: 20180247975Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Juan Saenz, Deepak Kamalanathan, Guangle Zhou, Ming-Che Wu, Tanmay Kumar
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Patent number: 10032908Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.Type: GrantFiled: January 6, 2017Date of Patent: July 24, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Perumal Ratnam, Christopher Petti, Juan Saenz, Guangle Zhou, Abhijit Bandyopadhyay, Tanmay Kumar
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Publication number: 20180197988Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.Type: ApplicationFiled: January 6, 2017Publication date: July 12, 2018Inventors: Perumal RATNAM, Christopher PETTI, Juan SAENZ, Guangle ZHOU, Abhijit BANDYOPADHYAY, Tanmay KUMAR
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Publication number: 20180166559Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, the word line including a first portion including a first conductive material and a second portion including a second conductive material, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, the semiconductor material layer disposed adjacent the second portion of the word line, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line.Type: ApplicationFiled: December 13, 2016Publication date: June 14, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Guangle Zhou, Chuanbin Pan, Juan Saenz, Tanmay Kumar
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Patent number: 9806256Abstract: A resistive memory device includes a first electrode, a sidewall spacer electrode located on a sidewall of a dielectric material contacting the first electrode, a resistive memory cell containing a resistive memory material and contacting the sidewall spacer electrode, and a second electrode containing the resistive memory cell.Type: GrantFiled: October 21, 2016Date of Patent: October 31, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Ming-Che Wu, Chuanbin Pan, Guangle Zhou, Tanmay Kumar
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Patent number: 9768180Abstract: A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, the word line layer including a first conductive material having a first work function, forming a nonvolatile memory material on a sidewall of the hole, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a local bit line in the hole, the local bit line including a second conductive material having a second work function, wherein the first work function is greater than the second work function, and forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer.Type: GrantFiled: October 29, 2016Date of Patent: September 19, 2017Assignee: SanDisk Technologies LLCInventors: Guangle Zhou, Yubao Li, Yangyin Chen, Tanmay Kumar
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Patent number: 9653617Abstract: A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p? region of the body. The TFT may have an n+ source and an n+ drain on either side of the p? region of the body. Thus, the TFT has an n+/p?/n+/p?/n+ structure in this example. The n+ layer in the p? region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p? body and/or thickness of the n+ layer in the p? body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n? region of the body. The TFT may have a p+ source and a p+ drain on either side of the p? region of the body.Type: GrantFiled: May 27, 2015Date of Patent: May 16, 2017Assignee: SanDisk Technologies LLCInventors: Guangle Zhou, Ming-Che Wu, Yung-Tin Chen
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Patent number: 9595530Abstract: A method is provided that includes forming a first vertical bit line disposed in a first direction above a substrate, forming a first word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, forming a first memory cell comprising a nonvolatile memory material at an intersection of the first vertical bit line and the first word line, forming a transistor above the substrate, and forming a first bit line select device coupled between the first vertical bit line and the transistor.Type: GrantFiled: July 7, 2016Date of Patent: March 14, 2017Assignee: SanDisk Technologies LLCInventor: Guangle Zhou
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Patent number: 9583615Abstract: A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer. Gate dielectrics and vertical semiconductor portions are sequentially formed on each patterned stack. Vertical semiconductor portions are removed from around the second patterned stack, while masked around the first patterned stack. Electrical dopants are introduced to top regions and bottom regions of the remaining vertical semiconductor portions to form a vertical switching device that includes the first patterned stack, while the second patterned stack functions as a horizontal interconnect structure. The vertical switching device can be a transistor or a gated diode.Type: GrantFiled: February 17, 2015Date of Patent: February 28, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yung-Tin Chen, Guangle Zhou, Christopher Petti
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Publication number: 20160351722Abstract: A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p? region of the body. The TFT may have an n+ source and an n+ drain on either side of the p? region of the body. Thus, the TFT has an n+/p?/n+/p?/n+ structure in this example. The n+ layer in the p? region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p? body and/or thickness of the n+ layer in the p? body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n? region of the body. The TFT may have a p+ source and a p+ drain on either side of the p? region of the body.Type: ApplicationFiled: May 27, 2015Publication date: December 1, 2016Applicant: SANDISK 3D LLCInventors: Guangle Zhou, Ming-Che Wu, Yung-Tin Chen
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Publication number: 20160240665Abstract: A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer. Gate dielectrics and vertical semiconductor portions are sequentially formed on each patterned stack. Vertical semiconductor portions are removed from around the second patterned stack, while masked around the first patterned stack. Electrical dopants are introduced to top regions and bottom regions of the remaining vertical semiconductor portions to form a vertical switching device that includes the first patterned stack, while the second patterned stack functions as a horizontal interconnect structure. The vertical switching device can be a transistor or a gated diode.Type: ApplicationFiled: February 17, 2015Publication date: August 18, 2016Inventors: Yung-Tin CHEN, Guangle Zhou, Christopher Petti
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Patent number: 8796733Abstract: A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.Type: GrantFiled: August 9, 2011Date of Patent: August 5, 2014Assignees: University of Notre Dame du Lac, International Business Machines CorporationInventors: Alan C. Seabaugh, Patrick Fay, Huili (Grace) Xing, Guangle Zhou, Yeqing Lu, Mark A. Wistey, Siyuranga Koswatta
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Publication number: 20120032227Abstract: A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.Type: ApplicationFiled: August 9, 2011Publication date: February 9, 2012Applicant: UNIVERSITY OF NOTRE DAME DU LACInventors: Alan C. SEABAUGH, Patrick FAY, Huili (Grace) XING, Guangle ZHOU, Yeqing LU, Mark A. WISTEY, Siyuranga KOSWATTA