Abstract: The present disclosure relates to the field of artificial intelligence (AI) and quantum technologies, and provides a quantum error correction hardware decoder and a chip. The quantum error correction hardware decoder includes: a memory storing instructions, a neural network processing unit, and a processor in communication with the memory and the neural network processing unit; and wherein, when the processor executes the instructions, the processor is configured to cause the quantum error correction decoder to: obtain error syndrome information for an error syndrome measured due to an error occurring in a quantum circuit, decode, by the neural network processing unit, the error syndrome information based on a neural network model to obtain an output result of the neural network model, and determine error information based on the output result, the error information indicating a qubit in which an error occurs in the quantum circuit and a corresponding error type.

Abstract: This application discloses a clock synchronization system, including a quantum control processor (QCP) and N digital/analog mutual conversion devices, each digital/analog mutual conversion device including a frequency conversion module and a signal synchronization module that includes a D flip-flop (DFF). The QCP generates a global synchronization signal and reference clock signals; and transmits the global synchronization signal and a reference clock signal to the frequency conversion module and transmits the global synchronization signal to the signal synchronization module of each conversion device. The frequency conversion module performs frequency conversion processing on the reference clock signal to obtain a target clock signal, and generates a signal synchronization instruction according to the global synchronization signal; and transmits the signal synchronization instruction and the target clock signal to the signal synchronization module.

Abstract: A quantum error correction (QEC) decoding system includes an error correction chip. The error correction chip is configured to: obtain error syndrome information of a quantum circuit; and decode the error syndrome information by running neural network decoders, to obtain error result information, a core operation of the neural network decoders being a multiply accumulate (MA) operation of unsigned fixed-point numbers obtained through numerical quantization. According to the present disclosure, for the system that uses the neural network decoders for QEC decoding, the core operation of the neural network decoders is the MA operation of unsigned fixed-point numbers obtained through numerical quantization, thereby minimizing the data volume and the calculation amount desirable by the neural network decoders, so as to better meet the requirement of real-time error correction.

Abstract: This application discloses a clock synchronization system, including a quantum control processor (QCP) and N digital/analog mutual conversion devices, each digital/analog mutual conversion device including a frequency conversion module and a signal synchronization module that includes a D flip-flop (DFF). The QCP generates a global synchronization signal and reference clock signals; and transmits the global synchronization signal and a reference clock signal to the frequency conversion module and transmits the global synchronization signal to the signal synchronization module of each conversion device. The frequency conversion module performs frequency conversion processing on the reference clock signal to obtain a target clock signal, and generates a signal synchronization instruction according to the global synchronization signal; and transmits the signal synchronization instruction and the target clock signal to the signal synchronization module.

Abstract: A quantum error correction (QEC) decoding system includes an error correction chip. The error correction chip is configured to: obtain error syndrome information of a quantum circuit; and decode the error syndrome information by running neural network decoders, to obtain error result information, a core operation of the neural network decoders being a multiply accumulate (MA) operation of unsigned fixed-point numbers obtained through numerical quantization. According to the present disclosure, for the system that uses the neural network decoders for QEC decoding, the core operation of the neural network decoders is the MA operation of unsigned fixed-point numbers obtained through numerical quantization, thereby minimizing the data volume and the calculation amount desirable by the neural network decoders, so as to better meet the requirement of real-time error correction.