Abstract: A shift register includes: an input circuit transmitting a first signal to a first node in response to a first clock signal and a second signal, transmitting the second signal to the first node in response to the first clock signal and the first signal; a first control circuit transmitting the first clock signal to a second node in response to the first node, transmitting a first voltage to the second node in response to the first clock signal; a second control circuit transmitting a second voltage to a third node in response to the first node, transmitting a second clock signal to the third node in response to the second node and the second clock signal; an output circuit transmitting the first voltage to a signal output terminal in response to the first node, transmitting the second voltage to the signal output terminal in response to the third node.

Abstract: A display panel and a display device are provided. The display panel includes: a pixel unit including a pixel circuit and a light-emitting element, the pixel circuit including a first transistor, the pixel unit including a first pixel unit and a second pixel unit located in a same row and adjacent columns; a first gate line and a second gate line, connected to gate electrodes of the first transistors of the first pixel unit and the second pixel unit; a first gate signal line, connected to the first pixel unit; a second gate signal line, connected to the second pixel unit; a first connection line connected with the first gate signal line through the first connection line; and a second connection line connected with the second gate signal line through the second connection line.

Abstract: A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit is configured to connect or disconnect the between an input terminal and the first input node under control of a clock signal provided by the clock signal terminal; the charge pump circuit is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal, so that a polarity of the voltage signal of the first input is the same as a polarity of the voltage signal of the first input node, and an absolute value of the voltage value of the voltage signal of the first node is greater than an absolute value of a voltage value of the voltage signal of the first input node.

Abstract: Disclosed in the embodiments of the present disclosure are a current detection device and a display device. The current detection device includes: a plurality of detection circuits; the detection circuit includes: a feedback compensation circuit and a current detection circuit; and the feedback compensation circuit is configured to generate a noise inversion signal by inverting a noise AC signal generated on the predetermined power line in the display panel and to provide the noise inversion signal to a first end of the current detection circuit; and the current detection circuit is configured to output a detection signal to the signal output end according to the noise inversion signal, the signal on the detection line and the signal of the reference voltage end.

Abstract: A gate driving unit, a gate driving circuit, a gate driving method, and a display device are provided. The gate driving unit includes a first output circuit and a second output circuit; the second output circuit comprises a first output sub-circuit; the first output circuit is respectively electrically connected to the first node, the second node and the first gate driving signal output end and is configured to control the first gate driving signal output end to output a first gate driving signal under the control of the potential of the first node and the potential of the second node; the first output sub-circuit is respectively electrically connected to the first node, the second gate driving signal output end and the first clock signal end, and is configured to control the second gate driving signal output end to be connected to the first clock signal end.

Abstract: Provided is a display substrate, the display substrate is provided with a display area and a peripheral area around the display area, and includes: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein in the peripheral area, the source/drain layer includes at least one pair of first signal lines including a signal line of a gate circuit and the anode layer includes a common power line provided with vent holes; and overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer. A display panel and a display device are also provided.

Abstract: A shift register circuit includes a denoising control sub-circuit and a denoising sub-circuit. The denoting control sub-circuit is configured to generate an alternating voltage signal according to a voltage of a first voltage terminal and a signal of a second clock signal terminal in response to a signal of a first clock signal terminal, to rectify the alternating voltage signal and then to output a signal to a first denoising control node, so that the voltage of the first denoting control node is maintained to be a voltage that enables the denoising sub-circuit to be turned on. The denoting sub-circuit is configured to denoise a scan signal output terminal in response to a voltage of the first denoising control node being the voltage that enables the denoising sub-circuit to be turned on.

Abstract: A shift register unit includes an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to provide signals of the signal input terminal to the first control node, and provide signals of the first power supply terminal or the first clock signal terminal to the second control node. The first control circuit is configured to provide signals of the second power supply terminal or the second clock signal terminal to the first output terminal. The second control circuit is configured to provide signals of the first power supply terminal to the second output terminal. The output circuit is configured to provide signals of the second power supply terminal to the second output terminal.

Abstract: A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.

Abstract: The present disclosure provides a signal generation circuit, a signal generation method, a signal generation module and a display device. The signal generating circuit includes an input terminal, a signal output terminal, a transmission control circuit, a first output circuit, and an output control circuit; the output control circuit is electrically connected to a first output control terminal, a second output control terminal, a second voltage terminal, the signal writing-in terminal, the signal output terminal and the first voltage terminal, configured to control to connect the signal writing-in terminal and the second voltage terminal under the control of a second output control signal provided by the second output control terminal, and control to connect the signal output terminal and the first voltage terminal under the control of a first output control signal provided by the first output control terminal. The present disclosure expands an adjustment range of frequency of a PWM signal.

Abstract: Provided are a gate driving circuit, a display substrate, a display device and a gate driving method, the gate driving circuit includes: a frequency doubling control circuit and an effective output circuit including first shift registers, the first shift register at the first stage has a first signal input terminal coupled with an output control signal line and a second signal input terminal coupled with the frequency doubling control circuit; the frequency doubling control circuit is coupled to the output control signal line, for providing a frequency doubling control signal thereto after a preset time period from the receipt of the output control signal in response to an output control signal from the output control signal line; the first shift register at the first stage outputs a scanning signal in response to the output control signal and a scanning signal in response to the frequency doubling control signal.

Abstract: A shift register includes: an input circuit transmitting a first signal to a first node in response to a first clock signal and a second signal, transmitting the second signal to the first node in response to the first clock signal and the first signal; a first control circuit transmitting the first clock signal to a second node in response to the first node, transmitting a first voltage to the second node in response to the first clock signal; a second control circuit transmitting a second voltage to a third node in response to the first node, transmitting a second clock signal to the third node in response to the second node and the second clock signal; an output circuit transmitting the first voltage to a signal output terminal in response to the first node, transmitting the second voltage to the signal output terminal in response to the third node.

Abstract: Embodiments of the present disclosure provide a shift register unit and a method foe driving the same, a gate driving circuit, and a display device. The shift register unit includes: a control circuit coupled to an input signal terminal, a clock signal terminal, and an output control terminal, and configured to provide an output control signal to the output control terminal based on a signal from the input signal terminal and a signal from the clock signal terminal; and an output circuit coupled to the output control terminal, an output signal terminal, and a threshold voltage control terminal, and configured to provide an output signal to the output signal terminal under control of a potential at the output control terminal, and adjust a threshold voltage of at least one of a plurality of transistors in the output circuit under control of a signal from the threshold voltage control terminal.

Abstract: The present application discloses a pixel array substrate. The pixel array substrate includes a plurality of pixels arranged in an array having multiple data-input terminals. N columns of subpixels per each column of pixels are associated with N sets of M numbers of data lines. N is an integer equal to and greater than 1 and M is an even number equal to or greater than 2. The pixel array substrate also includes N sets of M numbers of switches coupled respectively to the N sets of M numbers of data lines. Control terminals of each set of M numbers of switches are respectively coupled to M numbers of clock-signal terminals to receive respective clock control signals to control M groups of subpixels in each corresponding one column of subpixels for connecting with one of the multiple data-input terminals respectively via each corresponding set of M numbers of data lines.

Abstract: Embodiments of the present disclosure disclose a shift register unit, a driving method thereof, and a device. The shift register unit includes an input circuit, a node control circuit, a first control output circuit, a second control output circuit and an output circuit. By providing the first control output circuit and the second control output circuit, the first control output circuit and the second control output circuit may operate alternately, so that the first control output circuit and the second control output circuit may have time for characteristics recovery respectively, thus improving the service life and output stability of the shift register unit.

Abstract: Disclosed are a display panel and a display device. The display panel includes M rows and N columns of pixel units. The display panel is divided into R regions along a column direction, and an i-th region includes: (1+M(i?1)/R)-th row to a (Mi/R)-th row of pixel units. The display panel further includes M shift registers, M light emitting drivers, R light emitting control scan staring signal terminals, R scan start signal terminals for controlling time length and R scan start signal terminals for controlling current. An i-th row of pixel units is connected with an i-th shift register and an i-th light emitting driver, a light emitting driver connected to a first row of pixel units in the i-th region is connected with an i-th scan start signal terminal for controlling light emission.

Abstract: An organic light-emitting diode display substrate, a display panel and a display device. The display substrate includes a source/drain layer (101), a planarization layer (102) and an anode layer (103) which are laminated in sequence; the source/drain layer (101) comprises at least one pair of first signal lines (110); the anode layer (103) comprises a common power line (130), and the common power line (130) is provided with an air discharge hole (131); and the overlapping areas of a projection pattern of the air discharge hole (131) and two first signal lines (110) in any pair of first signal lines (110) are equal, the overlapping areas are greater than 0, and the projection pattern of the air discharge hole (131) is a pattern of an orthographic projection, on the source/drain layer (101), of the air discharge hole (131) on the common power line (130).

Abstract: A gate driving unit, a gate driving circuit, a gate driving method, and a display device are provided. The gate driving unit includes a first output circuit and a second output circuit; the second output circuit comprises a first output sub-circuit; the first output circuit is respectively electrically connected to the first node, the second node and the first gate driving signal output end and is configured to control the first gate driving signal output end to output a first gate driving signal under the control of the potential of the first node and the potential of the second node; the first output sub-circuit is respectively electrically connected to the first node, the second gate driving signal output end and the first clock signal end, and is configured to control the second gate driving signal output end to be connected to the first clock signal end.

Abstract: The present disclosure provides a gate driving unit, a gate driving method, a gate driving circuitry and a display device. The gate driving unit includes a reverse-phase gate driving signal output end, a normal-phase gate driving signal output end, an input circuitry, an output control circuitry, an input node control circuitry and an output circuitry. The input circuitry is configured to control an input end to be electrically connected to an input node under the control of a first clock signal. The output control circuitry is configured to control a potential at an output node under the control of a potential at the input node and a second clock signal. The input node control circuitry is configured to control the potential at the input node in accordance with the potential at the output node under the control of the second clock signal.

Abstract: The present disclosure is related to a flexible display panel. The flexible display panel may include a display substrate, a plurality of pixel units arranged in an array on the display substrate, and at least a strain sensor on the display substrate. The strain sensor may be arranged corresponding to a region comprising at least one of the plurality of pixel units. The strain sensor may be configured to detect deformation in the region comprising at least one of the plurality of pixel units and to generate a detection signal.