Abstract: A system and method for providing consistent performance in a storage device, such as a solid state drive. A threshold value for command execution time for a command in a category of command (e.g., a read command or a write command) and a command size, is stored in the storage device. When a host command in the category (e.g., a read command) and corresponding size is received, the storage device executes the command, and if it completes execution of the command in a time that is less than the threshold value, the solid state drive waits until an amount of time equal to the threshold value has elapsed before sending the command completion.

Abstract: A system and method for adaptive multiple read of NAND flash memory. A solid state drive may employ adaptive multiple-read to perform enhanced performance error correction using soft decisions without a performance penalty that otherwise might result from performing unnecessary reads. The soft decision error correcting algorithm may employ lookup tables containing log likelihood ratios. The method may include performing one or more read operations to obtain one or more raw data words for a code word, attempting to decode the code words using the one or more raw data words, and performing additional read operations when the decoding attempt fails. This process may be repeated until a decoding attempt succeeds.

Abstract: The invention discloses a novel quinazoline derivative LU1501 and a preparing method thereof, wherein the quinazoline derivative has a chemical name of N-[(4-fluorophenyl)methyl]-4-N-{7-methoxy-6-[(2-pyrrolidin-1-yl)hydroxyethyl]quinazoline-4-yl}phen-1,4-diamine. The quinazoline derivative and a pharmaceutically acceptable salt, a solvate and a hydrate thereof have excellent anti-tumor activity in vitro and in vivo to MCF-7, SK-BR-3, A549, HCT 116, U-118 MG, U-87 MG and MDA-MB-468, and have preferable application prospects on preparing anti-tumor drugs.

Abstract: The invention discloses a novel quinazoline derivative LU1501 and a preparing method thereof, wherein the quinazoline derivative has a chemical name of N-[(4-fluorophenyl)methyl]-4-N-{7-methoxy-6-[(2-pyrrolidin-1-yl)hydroxyethyl]quinazoline-4-yl}phen-1,4-diamine. The quinazoline derivative and a pharmaceutically acceptable salt, a solvate and a hydrate thereof have excellent anti-tumor activity in vitro and in vivo to MCF-7, SK-BR-3, A549, HCT 116, U-118 MG; U-87 MG and MDA-MB-468, and have preferable application prospects on preparing anti-tumor drugs.

Abstract: Embodiments of decoders having early decoding termination detection are disclosed. The decoders can provide for flexible and scalable decoding and early termination detection, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) decoding is used. In one embodiment, a decoder iteratively decodes a data unit using a decoding matrix comprising a plurality of layers. After at least one iteration of decoding the data unit, the decoder determines whether the decoded data unit from a completed iteration and one or more layers of the plurality of layers satisfy a parity check equation. In response to determining that the decoded data unit from the completed iteration and each layer of the plurality of layers satisfy the parity check equation, the decoder terminates decoding the data unit. Advantageously, the termination of decoding of the data unit can reduce a number of iterations performed to decode the data unit.

Abstract: A system and method for generating lookup tables for use in an adaptive multiple-read system for reading flash memory. Successive different attempts are made to decode previously stored data using error correction codes, the attempts differing, for example, with respect to the combination of raw data words used for each attempt, each raw data word having been obtained by reading a code word of data using a different word line voltage. When a decoding attempt succeeds, log likelihood ratios are calculated from counts of flipped bits, i.e., bits in the raw data read from the memory having a different value than the corresponding bits in the decoded data.

Abstract: Embodiments of solid-state storage devices provided herein include a voltage threshold calculation mechanism to calculate an optimal voltage read threshold for minimizing read errors. The system may be configured to determine optimal reference voltage value(s) by interpolating a pair of reads at two different threshold levels to determine the point that generates the least number of errors. In some cases, the evaluation may be an approximation based on a Cumulative Distribution Function (CDF) of errors of a first type and a second type. In other cases, the evaluation may be a calculation of an optimal voltage threshold based on the CDF of the errors. In yet other cases, the evaluation may be based on the Probability Density Function (PDF) of the errors.

Abstract: A system and method for providing consistent performance in a storage device, such as a solid state drive. A threshold value for command execution time for a command in a category of command (e.g., a read command or a write command) and a command size, is stored in the storage device. When a host command in the category (e.g., a read command) and corresponding size is received, the storage device executes the command, and if it completes execution of the command in a time that is less than the threshold value, the solid state drive waits until an amount of time equal to the threshold value has elapsed before sending the command completion.

Abstract: Embodiments of ECC encoders supporting multiple code rates and throughput speeds for data storage systems are disclosed. In one embodiment, an encoder can provide for flexible and scalable encoding, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) encoding is used. The encoder can be scaled in size based on, for example, the desired encoding throughput and/or computational cycle duration. The encoder can thus be used to support multiple code rates and throughput speeds. Accordingly, encoding speed and efficiency and system performance is improved.

Abstract: A method of restoring user data in a modular solid-state drive including memory channels coupled to respective ones of non-volatile memory cards, the method including: upon physical replacement of a defunct memory card of the non-volatile memory cards with a new non-volatile memory card, and power on of the modular solid-state drive, retrieving a firmware segment and a system segment of the modular solid-state drive from unaffected memory channels of the memory channels not coupled to the new non-volatile memory card; rebuilding a firmware of the modular solid-state drive based on the retrieved firmware segment; rebuilding a data mapping table associated with the non-volatile memory cards based on the retrieved system segment; and restoring full integrity of the user data originally stored on the non-volatile memory cards based on the rebuilt data mapping table and data from the unaffected memory channels.

Abstract: Error Correction Codes, which are able to take soft-decision information, work much better when compared with hard-decision decoding. It can achieve much better performance. However, due to lack of direct soft-decision information for the NAND flash, multiple-reads with different voltage thresholds are used to generate the soft-decision information. Another invention disclosure describes a method to perform the multiple-read adaptively with different voltage threshold for the NAND flash in order to minimize the number of total multiple-read. The invention disclosure described here is a method of flash channel calibration, which will generate multiple LUTs for adaptive multiple-read with different voltage threshold.

Abstract: The solution described here is a method to provide consistent performance in a storage device. A performance manager module is implemented to measure the time interval in which a command takes to be completed. In case the time interval is longer than a certain threshold, the difference is annotated and used on the consecutive commands within a programmable time window. This time window can be a regular time interval e.g. every second. In case the time interval is shorter than a threshold, the control module delays sending the command completion to the host until the threshold value is reached. The delay is adjusted based on the credit annotation due to commands that took longer than the time interval to be completed in order to compensate for commands that took longer than the threshold to complete, during a certain time window.

Abstract: The solution described here is a method to rebuild channel content via RAID approach in the field after one channel is replaced by a new flash channel module depicted in “Invention Disclosure Form-UHC”.

Abstract: Embodiments of ECC encoders supporting multiple code rates and throughput speeds for data storage systems are disclosed. In one embodiment, an encoder can provide for flexible and scalable encoding, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) encoding is used. The encoder can be scaled in size based on, for example, the desired encoding throughput and/or computational cycle duration. The encoder can thus be used to support multiple code rates and throughput speeds. Accordingly, encoding speed and efficiency and system performance is improved.

Abstract: A data storage system configured to adaptively code data and related methods are disclosed. In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller includes a channel monitor that determines the quality of read signals from the pages when they are read, and provides adjustment metrics to aid in the selection of a code rate, such as a code rate for a low-density parity-check (LDPC) code. In this way, the code rate used for data encoding can be dynamically adjusted to accommodate degradation of the non-volatile memory array over its useable life.

Abstract: Embodiments of ECC encoders supporting multiple code rates and throughput speeds for data storage systems are disclosed. In one embodiment, an encoder can provide for flexible and scalable encoding, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) encoding is used. The encoder can be scaled in size based on, for example, the desired encoding throughput and/or computational cycle duration. The encoder can thus be used to support multiple code rates and throughput speeds. Accordingly, encoding speed and efficiency and system performance is improved.

Abstract: The invention relates to the technical field of an alignment method, and discloses a method for aligning substrate and mask, including: firstly forming at least one set of alignment marks on a mask plate; selecting a certain number of large-size substrates as sample substrates; forming a plurality of sets of alignment marks on each sample substrate using the mask plate and the at least one set of alignment marks formed thereon to divide the sample substrate into a plurality of sub-substrate areas; and then performing mask process on the respective sample substrates, accurate alignment for each sub-substrate area can be realized by means of the plurality of sets of alignment marks on the sample substrate, and one sub-substrate area can be accurately aligned by means of at least two sets of alignment marks formed on the sample substrate.

Abstract: A data storage system configured to implement a data reliability scheme is disclosed. In one embodiment, a data storage system controller detects uncorrectable errors using intra page parity when data units are read from a set of pages. When an uncorrectable error is detected, the data storage system controller attempts to recover user data using inter page parity without using all data from each page of the set of pages. Recovery of user data can thereby be performed without reading all data from each page. As a result, the amount of time needed to read data can be reduced in some cases and overall data storage system performance can be increased.

Abstract: A data storage system configured to adaptively code data is disclosed. In one embodiment, a data storage system controller determines a common memory page size, such as an E-page size, for a non-volatile memory array. Based on the common memory page size, the controller selects a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths. The controller determines LDPC coding parameters for coding data written to or read from the memory array based on the selected LDPC code word length. By using the plurality of pre-defined LDPC code word lengths, the data storage system can support multiple non-volatile memory page formats, including memory page formats in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths. Flexibility and efficiency of data coding can thereby be achieved.

Abstract: A data storage system configured to adaptively code data is disclosed. In one embodiment, a data storage system controller determines a common memory page size, such as an E-page size, for a non-volatile memory array. Based on the common memory page size, the controller selects a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths. The controller determines LDPC coding parameters for coding data written to or read from the memory array based on the selected LDPC code word length. By using the plurality of pre-defined LDPC code word lengths, the data storage system can support multiple non-volatile memory page formats, including memory page formats in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths. Flexibility and efficiency of data coding can thereby be achieved.