Abstract: The invention discloses a high-voltage LDMOS integrated device, which is interdigitally structured in a plan view and which including: a first area corresponding to a source fingertip area, wherein a first sectional structure of the first area particularly includes: a first drain; and a first longitudinal voltage-withstanding buffer layer located below the first drain and consisted of a first deep N-well and a first low-voltage N-well, wherein the first low-voltage N-well is located in the first deep-N well, and the first deep-N well is located in a P-type substrate; and a second area non-overlapping with the first area, wherein a second sectional structure of the second area particularly includes: a second drain; and a second longitudinal voltage-withstanding buffer layer located below the second drain and consisted of a second deep N-well and a second low-voltage N-well.

Abstract: The invention provides a method for fabricating a transistor and a transistor, wherein the method for fabricating a transistor includes: growing a second oxide layer on the surface of a substrate on which a first oxide layer and a first base region are formed, wherein the second oxide layer is formed above the first base region; forming an emitter region in a first preset area on the second oxide layer; forming a contact hole in a second preset area on the second oxide layer, wherein the second preset area does not overlap with the first preset area; injecting doping elements into the surface of the first base region in the area of the contact hole; and thermally processing the substrate to activate the doping elements to form a second base region.

Abstract: A method for manufacturing an IGBT includes: forming oxide layers on the surfaces of the front and the back of an N-type substrate; forming a buffer layer in the surface of the back of the N-type substrate; forming protection layers on the surfaces of the oxide layers; removing the protection layer and the oxide layer overlying the front of the N-type substrate while reserving the oxide layer and the protection layer on the back of the N-type substrate for protection of the back of the N-type substrate; forming a front IGBT structure and applying a protection film on the surface of the front IGBT structure for protection of the front IGBT structure; removing the protection layer and the oxide layer overlying the back of the N-type substrate; forming a back IGBT structure and a back metal layer; and removing the protection film overlying the surface of the front IGBT structure.

Abstract: A method for manufacturing an IGBT includes: forming oxide layers on the surfaces of the front and the back of an N-type substrate; forming a buffer layer in the surface of the back of the N-type substrate; forming protection layers on the surfaces of the oxide layers; removing the protection layer and the oxide layer overlying the front of the N-type substrate while reserving the oxide layer and the protection layer on the back of the N-type substrate for protection of the back of the N-type substrate; forming a front IGBT structure and applying a protection film on the surface of the front IGBT structure for protection of the front IGBT structure; removing the protection layer and the oxide layer overlying the back of the N-type substrate; forming a back IGBT structure and a back metal layer; and removing the protection film overlying the surface of the front IGBT structure.

Abstract: The invention relates to the field of fabricating a semiconductor integrated circuit and particularly to an integrated device and a method for fabricating the integrated device in order to address the problem that a drift area is fabricated on an epitaxial layer but the application scope of the LDMOS is limited due to the costly process of fabricating the epitaxial layer. An integrated device of an nLDMOS and a pLDMOS according to an embodiment of the invention includes a substrate and further includes an nLDMOS and a pLDMOS, where the nLDMOS and the pLDMOS are located in the substrate. The nLDMOS and the pLDMOS is located in the substrate without any epitaxial layer, thereby lowering the fabrication cost and extending the application scope.

Abstract: The invention discloses a high-voltage LDMOS integrated device, which is interdigitally structured in a plan view and which including: a first area corresponding to a source fingertip area, wherein a first sectional structure of the first area particularly includes: a first drain; and a first longitudinal voltage-withstanding buffer layer located below the first drain and consisted of a first deep N-well and a first low-voltage N-well, wherein the first low-voltage N-well is located in the first deep-N well, and the first deep-N well is located in a P-type substrate; and a second area non-overlapping with the first area, wherein a second sectional structure of the second area particularly includes: a second drain; and a second longitudinal voltage-withstanding buffer layer located below the second drain and consisted of a second deep N-well and a second low-voltage N-well.

Abstract: The invention discloses a method for manufacturing a dual-layer polysilicon gate. The method includes: depositing silicon nitride on silicon oxide of an integrated circuit to be processed; performing anisotropic etching on the silicon nitride to form sidewalls of silicon nitride on sidewalls of a first layer of polysilicon gate of the integrated circuit to be processed; manufacturing a second layer of polysilicon gate; and rinsing the sidewalls of silicon nitride.