Patents by Inventor Guangren LI

Guangren LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11216393
    Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: January 4, 2022
    Assignee: LONTIUM SEMICONDUCTOR CORPORATION
    Inventors: Xianghao Guo, Chuanxing Liu, Feng Chen, Hongfeng Xia, Jin Su, Haowei Guan, Diansheng Ren, Lianliang Tai, Dafeng Zhou, Guangren Li, Changqian Xie
  • Publication number: 20210311886
    Abstract: A conversion apparatus, a storage device and a method for manufacturing the same are provided. The storage device may include a DDR storage layer, a DDR interface layer, a conversion logic circuit layer, and a peripheral interface layer. The peripheral interface layer may include a GDDR interface layer or a PCIe interface layer. The conversion logic circuit layer may process, by using DDR storage logic, data obtained through the peripheral interface layer and transfer processed data to the DDR interface layer, or process, by using GDDR storage logic, data obtained through the DDR interface layer and transfer processed data to the peripheral interface Layer. The DDR storage layer may be connected to the DDR interface layer, so that the conversion logic circuit layer can convert the storage logic of the data from DDR to GDDR or from GDDR to DDR.
    Type: Application
    Filed: May 12, 2020
    Publication date: October 7, 2021
    Applicant: LONTIUM SEMICONDUCTOR CORPORATION
    Inventors: Xianghao GUO, Chuanxing LIU, Feng CHEN, Hongfeng XIA, Jin SU, Haowei GUAN, Diansheng REN, Lianliang TAI, Dafeng ZHOU, Guangren LI, Changqian XIE
  • Patent number: 9104822
    Abstract: A signal transmission method for a USB interface and an apparatus thereof are provided. The method includes: receiving a first USB signal sent from a sending terminal, processing the first USB signal into a USB-like signal, and transmitting the USB-like signal via a networking cable; receiving the USB-like signal, processing the USB-like signal into a second USB signal, and sending the second USB signal to a receiving terminal. According to the embodiments of the present invention, the first USB signal is processed into a USB-like signal which is similar to the USB signal, the USB-like signal is transmitted via a networking cable, and the USB-like signal is processed into a second USB signal. The transmission process does not require converting the USB signal into a networking-cable signal which is to be transmitted via a networking cable, thereby avoiding conversion between protocols, and simplifying the entire transmission process.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: August 11, 2015
    Assignee: LONTIUM SEMICONDUCTOR CORPORATION
    Inventors: Jiaxi Fu, Hui Bian, Shengquan Hu, Lianliang Tai, Feng Chen, Chaoqun Chu, Qingwei Liu, Guangren Li
  • Patent number: 8934591
    Abstract: The present invention provides a clock and data recovery circuit, including an n-phase clock, a sampling and edge detection unit, an edge determination unit, a clock picking unit and a data picking unit. The sampling and edge detection unit performs spaced sampling on the input serial data using the n-phase clock, and performs edge detection and resampling on the sampled data. The edge determination unit filters the resampled data by the counting units, and obtains the positions of the edges of the serial data according to the counting result of the counting units. The clock picking unit selects a clock from the n clocks that is the farthest away from the edges as the recovered clock. The data picking unit obtains the recovered data according to the recovered clock. The present invention also provides a parallel output circuit.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: January 13, 2015
    Assignee: Lontium Semiconductor Corporation
    Inventors: Lianliang Tai, Guangren Li, Feng Chen
  • Publication number: 20140075070
    Abstract: A signal transmission method for a USB interface and an apparatus thereof are provided. The method includes: receiving a first USB signal sent from a sending terminal, processing the first USB signal into a USB-like signal, and transmitting the USB-like signal via a networking cable; receiving the USB-like signal, processing the USB-like signal into a second USB signal, and sending the second USB signal to a receiving terminal. According to the embodiments of the present invention, the first USB signal is processed into a USB-like signal which is similar to the USB signal, the USB-like signal is transmitted via a networking cable, and the USB-like signal is processed into a second USB signal. The transmission process does not require converting the USB signal into a networking-cable signal which is to be transmitted via a networking cable, thereby avoiding conversion between protocols, and simplifying the entire transmission process.
    Type: Application
    Filed: February 7, 2013
    Publication date: March 13, 2014
    Applicant: Lontium Semiconductor Corporation
    Inventors: Jiaxi FU, Hui BIAN, Shengquan HU, Lianliang TAI, Feng CHEN, Chaoqun CHU, Qingwei LIU, Guangren LI
  • Publication number: 20130163706
    Abstract: The present invention provides a clock and data recovery circuit, including an n-phase clock, a sampling and edge detection unit, an edge determination unit, a clock picking unit and a data picking unit. The sampling and edge detection unit performs spaced sampling on the input serial data using the n-phase clock, and performs edge detection and resampling on the sampled data. The edge determination unit filters the resampled data by the counting units, and obtains the positions of the edges of the serial data according to the counting result of the counting units. The clock picking unit selects a clock from the n clocks that is the farthest away from the edges as the recovered clock. The data picking unit obtains the recovered data according to the recovered clock. The present invention also provides a parallel output circuit.
    Type: Application
    Filed: December 27, 2012
    Publication date: June 27, 2013
    Inventors: Lianliang TAI, Guangren LI, Feng CHEN