Patents by Inventor Guangyi LU

Guangyi LU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transient-triggered DC voltage-sustained power-rail ESD clamp circuit
    Patent number: 10096994
    Abstract: A transient-triggered DC voltage-sustained power-rail ESD clamp circuit comprises: a transient-triggered module, a DC voltage-triggered module and a discharge device, wherein the transient-triggered module is connected with the DC voltage-triggered module and the discharge device respectively. When an ESD event is approaching, the ESD protection circuit can be turned on well and quickly, and can effectively avoid the problems of erroneous triggering and latching-up caused by quick power-on and high-frequency noise at the same time.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: October 9, 2018
    Assignee: PEKING UNIVERSITY
    Inventors: Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang
  • False-trigger free power-rail ESD clamp protection circuit
    Patent number: 9531188
    Abstract: A false-trigger free power-rail ESD clamp protection circuit includes an ESD impact detection component, a discharge transistor, a discharge transistor turn-on channel, and a discharge transistor shutoff channel. The circuit, in a smaller layout area, has very strong electrostatic charge discharge capability under ESD impact, little power leakage during normal power-up, and relatively strong false-trigger immunity capability for quick power-up.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: December 27, 2016
    Assignee: Peking University
    Inventors: Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang
  • TRANSIENT-TRIGGERED DC VOLTAGE-SUSTAINED POWER-RAIL ESD CLAMP CIRCUIT
    Publication number: 20160087429
    Abstract: A transient-triggered DC voltage-sustained power-rail ESD clamp circuit comprises: a transient-triggered module, a DC voltage-triggered module and a discharge device, wherein the transient-triggered module is connected with the DC voltage-triggered module and the discharge device respectively. When an ESD event is approaching, the ESD protection circuit can be turned on well and quickly, and can effectively avoid the problems of erroneous triggering and latching-up caused by quick power-on and high-frequency noise at the same time.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 24, 2016
    Inventors: Yuan WANG, Guangyi LU, Jian CAO, Xing ZHANG
  • FALSE-TRIGGER FREE POWER-RAIL ESD CLAMP PROTECTION CIRCUIT
    Publication number: 20150295399
    Abstract: A false-trigger free power-rail ESD clamp protection circuit includes an ESD impact detection component, a discharge transistor, a discharge transistor turn-on channel, and a discharge transistor shutoff channel. The circuit, in a smaller layout area, has very strong electrostatic charge discharge capability under ESD impact, little power leakage during normal power-up, and relatively strong false-trigger immunity capability for quick power-up.
    Type: Application
    Filed: November 20, 2013
    Publication date: October 15, 2015
    Inventors: Yuan WANG, Guangyi LU, Jian CAO, Xing ZHANG