Patents by Inventor Guanhua Hou

Guanhua Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240181596
    Abstract: The polishing pad has a polymeric matrix, a polishing surface useful for polishing at least one of semiconductor, magnetic and optical substrates and a bottom surface; a porous subpad adhered to the bottom surface of the polishing pad. The porous subpad includes a nonporous microlayer for securing the polishing pad to the porous subpad. The porous polymer network contains i) a single layer of closed cell micropores adjacent the nonporous microlayer for transitioning compressive forces from the bottom surface of the polishing pad to the porous subpad; and ii) a multilayer of closed cell, open cell or a mixture of closed and open cell micropores adjacent the single layer of closed cell micropores.
    Type: Application
    Filed: October 19, 2023
    Publication date: June 6, 2024
    Inventors: Guanhua Hou, Bryan E. Barton, Alaaeddin Alsbaiee, Andrew Wank, Techun Wang, Annette M. Crevasse, Nestor A. Vasquez, John R. McCormick
  • Publication number: 20240181597
    Abstract: The invention provides a porous subpad for a chemical mechanical polishing pad comprising a polishing layer having a polymeric matrix, a polishing surface useful for polishing at least one of semiconductor, magnetic and optical substrates and a bottom surface. The porous subpad includes a non-porous layer having a polymeric matrix and a multilayer having a micro-scale negative impression of the bottom surface of the polishing pad. The multilayer is closed cell, open cell or a mixture of closed and open cell micropores that are gas filled; and the multilayer remains gas filled during an entire polishing life of the polishing pad.
    Type: Application
    Filed: October 19, 2023
    Publication date: June 6, 2024
    Inventors: Guanhua Hou, Andrew Wank, Techun Wang, Nestor A. Vasquez, John R. McCormick
  • Patent number: 11325221
    Abstract: The invention provides a polishing pad suitable for polishing integrated circuit wafers. It includes an upper polishing layer that having a polishing surface and at least one groove in the upper polishing layer. At least one transparent window is located within the upper layer. The at least one transparent window has a thickness greater than a desired wear depth of the at least one groove. The at least one transparent window includes a non-fluorescent transparent polymer; and a fluorescent transparent polymer. The transparent window allows measuring groove depth by activating the fluorescent transparent polymer with an activation source at a wavelength sufficient to excite the fluorescent transparent polymer and allow endpoint detection by sending light through the fluorescent transparent polymer and the non-fluorescent transparent polymer.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: May 10, 2022
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Matthew R. Gadinski, Mauricio E. Guzman, Nestor A. Vasquez, Guanhua Hou
  • Patent number: 11192215
    Abstract: The invention provides a polishing pad suitable for polishing integrated circuit wafers. A polyurethane polishing layer has a top surface and at least one groove in the polyurethane polishing layer. At least one copolymer wear detector located within the polyurethane polishing layer detects wear of the polishing layer adjacent the at least one groove. The at least one wear detector includes two regions, a first region being a fluorescent acrylate/urethane copolymer linked with a UV curable linking group and a second non-fluorescent region, The wear detector allows detecting wear of the polishing layer.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 7, 2021
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Mauricio E. Guzman, Matthew R. Gadinski, Nestor A. Vasquez, Guanhua Hou
  • Publication number: 20190232459
    Abstract: The invention provides a polishing pad suitable for polishing integrated circuit wafers. It includes an upper polishing layer that having a polishing surface and at least one groove in the upper polishing layer. At least one transparent window is located within the upper layer. The at least one transparent window has a thickness greater than a desired wear depth of the at least one groove. The at least one transparent window includes a non-fluorescent transparent polymer; and a fluorescent transparent polymer. The transparent window allows measuring groove depth by activating the fluorescent transparent polymer with an activation source at a wavelength sufficient to excite the fluorescent transparent polymer and allow endpoint detection by sending light through the fluorescent transparent polymer and the non-fluorescent transparent polymer.
    Type: Application
    Filed: November 9, 2018
    Publication date: August 1, 2019
    Inventors: Matthew R. Gadinski, Mauricio E. Guzman, Nestor A. Vasquez, Guanhua Hou
  • Publication number: 20190224811
    Abstract: The invention provides a polishing pad suitable for polishing integrated circuit wafers. A polyurethane polishing layer has a top surface and at least one groove in the polyurethane polishing layer. At least one copolymer wear detector located within the polyurethane polishing layer detects wear of the polishing layer adjacent the at least one groove. The at least one wear detector includes two regions, a first region being a fluorescent acrylate/urethane copolymer linked with a UV curable linking group and a second non-fluorescent region, The wear detector allows detecting wear of the polishing layer.
    Type: Application
    Filed: November 9, 2018
    Publication date: July 25, 2019
    Inventors: Mauricio E. Guzman, Matthew R. Gadinski, Nestor A. Vasquez, Guanhua Hou