Abstract: A device includes a first vertical stack of first nanostructures formed over a substrate, a second vertical stack of second nanostructures adjacent to the first vertical stack, and a first gate structure adjacent the first nanostructures. The first gate structure includes a first gate portion between the first nanostructures, and a second gate portion extending from a first sidewall of the first gate portion to a second sidewall of the first gate portion. The second sidewall is between the first sidewall and the substrate, and is a different material than the first gate portion. A second gate structure is adjacent the second nanostructures, and a second wall structure is between the second gate portion and the second gate structure.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region, a contact etch stop layer disposed over the source/drain region, a first interlayer dielectric (ILD) layer disposed over the contact etch stop layer, an etch stop layer disposed over the contact etch stop layer and the first ILD layer, a second ILD layer disposed over the etch stop layer, a substrate portion disposed below the source/drain region, and an isolation region disposed adjacent the substrate portion. The isolation region includes a first dielectric layer including a first dielectric material and a second dielectric layer disposed on the first dielectric layer. The second dielectric layer includes a second dielectric material different from the first dielectric material. The isolation region further includes a hard mask structure disposed on the first and second dielectric layers.

Abstract: A vertically protruding structure is formed. The vertically protruding structure includes a substrate, a first semiconductor layer disposed over the substrate, a channel layer disposed over the first semiconductor layer, and a second semiconductor layer disposed over the channel layer. The first semiconductor layer and the second semiconductor layer each contain a first type of semiconductive material. The channel layer contains a second type of semiconductive material different from the first type. First recesses are formed in the first semiconductor layer and the second semiconductor layer. Each of the first recesses protrudes laterally inward. The first recesses are filled with dielectric spacers. The channel layer and the substrate are laterally trimmed. The remaining portions of the channel layer and the dielectric spacers define second recesses that protrude laterally inward. Gate structures are formed in the second recesses.

Abstract: A method for manufacturing a semiconductor device is provided with the following steps. A plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on a substrate are formed. Edge portions of the second semiconductor layers are removed to form a plurality of semiconductor nanosheets between the first semiconductor layers. A plurality of semipermeable films is formed on sidewalls of the semiconductor nanosheets. The semiconductor nanosheets is removed to form a plurality of cavities between the first semiconductor layers. A plurality of sacrificial dielectric layers is deposited in the cavities defined by the semipermeable films.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: A semiconductor memory device includes a first dielectric wall, a second dielectric wall, first channel portions, second channel portions, an isolation wall, and a dielectric feature. The second dielectric wall is spaced apart from the first dielectric wall in a first direction. The first channel portions are disposed on a side of the first dielectric wall and are spaced apart from each other in a second direction transverse to the first direction. The second channel portions are disposed on a side of the second dielectric wall and are spaced apart from each other in the second direction. The isolation wall is located between the first dielectric wall and the second dielectric wall. The dielectric feature is disposed to separate the first dielectric wall and the isolation wall, and is disposed on the other side of the first dielectric wall opposite to the first channel portions in the first direction.

Abstract: A method includes forming an epitaxial stack including a first sacrificial layer, a channel layer, and a second sacrificial layer over a semiconductor substrate; patterning the epitaxial stack into a fin structure such that opposite first ends of the channel layer are exposed; recessing the opposite first ends of the channel layer; forming first dummy spacers on the recessed opposite first ends of the channel layer; forming an isolation structure in the fin structure; recessing a top surface of the isolation structure to a position lower than a bottom surface of the channel layer, such that opposite second ends of the channel layer are exposed; recessing the opposite second ends of the channel layer; forming second dummy spacers on the recessed opposite second ends of the channel layer; and replacing the first dummy spacers and the second dummy spacers with a metal gate structure.

Abstract: A device includes a first stack of nanostructures formed over a substrate; a second stack of nanostructures formed adjacent to the first stack; a first gate structure on the nanostructures of the first stack; a second gate structure on the nanostructures of the second stack; a first insulating wall separating the first gate structure and the second gate structure; a hard mask layer on the first gate structure and on the second gate structure; and a gate contact extending through the hard mask layer to physically and electrically contact the first gate structure.

Abstract: A method of forming a semiconductor device comprises the following steps. A multi-layer stack is formed over a substrate. The multi-layer stack comprises alternately stacked first semiconductor layers and second semiconductor layers. A dielectric protective layer is formed over the multi-layer stack. Gate spacers are formed over the dielectric protective layer. A first portion of the dielectric protective layer is removed from a top surface of the multi-layer stack, while leaving second portions of the dielectric protective layer under the gate spacer. The first semiconductor layers are replaced with a metal gate stack. A gate contact is formed over the metal gate stack.

Abstract: A method for manufacturing a semiconductor device is provided, including the following steps. A first protective layer and a second protective layer are formed on top of a stack of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately disposed. The second semiconductor layers are removed to form at least one cavity between the first semiconductor layers. A sacrificial dielectric layer and a plurality of dielectric spacers are formed between the first semiconductor layers. The sacrificial dielectric layer located under the second protective layer is removed to form a first cavity. The sacrificial dielectric layer between the first semiconductor layers is removed to form a second cavity. The second protective layer exposed in the first cavity is removed so that the height of the first cavity is greater than the height of the second cavity.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first protrusion over a substrate, a first plurality of nanostructures vertically stacked over the first protrusion, and a dielectric feature and an isolation structure over the substrate. The first protrusion is located between the dielectric feature and the isolation structure. The semiconductor structure further includes a plurality of spacer features interposed between the dielectric feature and the first plurality of nanostructures, and a gate dielectric layer wrapping around the first plurality of nanostructures. The gate dielectric layer extends along a top surface of the isolation structure.

Abstract: A semiconductor structure includes a first stack of semiconductor layers disposed over a semiconductor substrate, where the first stack of semiconductor layers includes a first SiGe layer and a plurality of Si layers disposed over the first SiGe layer and the Si layers are substantially free of Ge, and a second stack of semiconductor layers disposed adjacent to the first stack of semiconductor layers, where the second stack of semiconductor layers includes the first SiGe layer and a plurality of second SiGe layers disposed over the first SiGe layer, and where the first SiGe layer and the second SiGe layers have different compositions. The semiconductor structure further includes a first metal gate stack interleaved with the first stack of semiconductor layers to form a first device and a second metal gate stack interleaved with the second stack of semiconductor layers to form a second device different from the first device.

Abstract: A semiconductor device includes a substrate, channel layers disposed over the substrate, a gate structure disposed on the substrate and wrapping around the channel layers, and source/drain structures disposed besides the channel layers and at opposite sides of the gate structure. The channel layers are spaced apart from one another. The gate structure comprises an upper gate feature and interposing gate features between the channel layers. The interposing gate features comprise protrusions protruding into the channel layers.

Abstract: A method for forming a semiconductor structure includes alternately forming a plurality of channel layers and a plurality of sacrificial layers over a substrate. The method includes forming a top sacrificial layer over the channel layers and the sacrificial layers. The method includes forming a source/drain trench through the top sacrificial layer, the channel layers, and the sacrificial layers. The method includes recessing the top sacrificial layer and the sacrificial layers through the source/drain trench so that a first width of the top sacrificial layer is less than a second width of the sacrificial layers. The method includes forming a plurality of inner spacers on sidewalls of the top sacrificial layer and sidewalls of the sacrificial layers. The method includes replacing the top sacrificial layer and the sacrificial layers with a gate structure.

Abstract: Embodiments of the present disclosure provide a semiconductor device structure and methods for forming the same. The structure includes a first semiconductor layer disposed in a first region and a second semiconductor layer surrounding the first semiconductor layer in the first region. The first and second semiconductor layers comprise different materials. The structure further includes a first gate electrode layer surrounding a portion of the second semiconductor layer, a first source/drain region electrically connected to the second semiconductor layer, and a second source/drain region electrically connected to the second semiconductor layer. The second semiconductor layer is disposed between the first and second source/drain regions.

Abstract: A device includes a stack of first semiconductor nanostructures over a substrate and a stack of second semiconductor nanostructures over the substrate. The device includes an isolation structure between the first and second semiconductor nanostructures. The isolation structure includes a core dielectric layer extending from below a top surface of the substrate to a level higher than all of the first and second semiconductor nanostructures. The isolation structure includes a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface lower than all of the semiconductor nanostructures. The spaces between the core dielectric layer and each of the semiconductor nanostructures can be filled with gate dielectric material or with remnants of the shell dielectric layer.

Abstract: A device includes a plurality of nanosheets over a substrate, a source/drain feature adjacent to the plurality of nanosheets, and a gate structure disposed over the plurality of nanosheets and between adjacent nanosheets. Gate spacers are disposed over sidewalls of opposing sides of a top portion of the gate structure. Inner spacers interpose lateral ends of adjacent ones of the plurality of nanosheets in a first direction and interpose portions of the gate structure and the source/drain feature in a second direction. Each of the inner spacers includes a core layer and a liner layer disposed on a top and bottom surfaces of the core layer. There is an offset of a dimension of the plurality of nanosheets in a third direction at an interface between portions of the nanosheets underneath the gate spacers and portions of the nanosheets underneath the top portion of the gate structure.

Abstract: Various embodiments of the present disclosure provide a method for forming a semiconductor device structure. In one embodiment, the method includes forming a fin over a substrate, wherein the fin comprises first semiconductor layers and second semiconductor layers alternating stacked. The method also includes forming a sacrificial gate structure over the fin, removing portions of the fin not covered by the sacrificial gate structure, replacing the second semiconductor layers with a sacrificial dielectric material, recessing edge portions of the sacrificial dielectric material to form cavities between the first semiconductor layers, forming a dielectric spacer in the cavities by depositing a conformal layer of a dielectric liner layer on exposed surfaces of each cavity, forming source/drain features on opposite sides of the sacrificial gate structure, and replacing the sacrificial gate structure and the sacrificial dielectric material with a gate structure wrapping around the first semiconductor layers.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: A method of forming a semiconductor structure includes forming a fin structure including first and second semiconductor layers that are alternately stacked; forming a dummy gate structure on the fin structure; and forming source/drain trenches on opposite sides of the dummy gate structure. The method further includes removing the first semiconductor layers through the source/drain trenches to form cavities; epitaxially growing epitaxial layers on surfaces of the second semiconductor layers exposed in the cavities; and forming dielectric layers to fill the cavities, such that the dielectric layers are between the second semiconductor layers, between the substrate and the bottommost second semiconductor layer, and over the topmost second semiconductor layer. The method further includes removing the dummy gate structure to form a gate trench; trimming the second semiconductor layers and the dielectric layers through the gate trench; and forming a gate structure in the gate trench.