Patents by Inventor Guannan Liu
Guannan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12205947Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.Type: GrantFiled: June 7, 2023Date of Patent: January 21, 2025Assignee: Intel CorporationInventors: Guannan Liu, Akm A. Ahsan, Mark Armstrong, Bernhard Sell
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Patent number: 11977137Abstract: A method may include obtaining image data of a subject acquired by an imaging device. The method may also include determining one or more characteristics associated with a body part of the subject from the image data. The one or more characteristics of the body part of the subject may include at least one of position information of the body part in the subject, geometric morphology information of the body part, water content information, or fat content information. The method may also include determining, based on one or more characteristics associated with the body part, values of one or more individualized parameters corresponding to the subject. The method may further include causing the imaging device to perform an imaging scan on the subject according to the values of the one or more individualized parameters.Type: GrantFiled: April 8, 2022Date of Patent: May 7, 2024Assignee: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.Inventors: Liu Liu, Guannan Liu
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Publication number: 20230317720Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventors: Guannan LIU, Akm A. AHSAN, Mark ARMSTRONG, Bernhard SELL
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Patent number: 11728335Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.Type: GrantFiled: January 25, 2019Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Guannan Liu, Akm A. Ahsan, Mark Armstrong, Bernhard Sell
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Patent number: 11515424Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.Type: GrantFiled: February 8, 2019Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Said Rami, Hyung-Jin Lee, Saurabh Morarka, Guannan Liu, Qiang Yu, Bernhard Sell, Mark Armstrong
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Publication number: 20220236348Abstract: A method may include obtaining image data of a subject acquired by an imaging device. The method may also include determining one or more characteristics associated with a body part of the subject from the image data. The one or more characteristics of the body part of the subject may include at least one of position information of the body part in the subject, geometric morphology information of the body part, water content information, or fat content information. The method may also include determining, based on one or more characteristics associated with the body part, values of one or more individualized parameters corresponding to the subject. The method may further include causing the imaging device to perform an imaging scan on the subject according to the values of the one or more individualized parameters.Type: ApplicationFiled: April 8, 2022Publication date: July 28, 2022Applicant: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.Inventors: Liu LIU, Guannan LIU
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Patent number: 11313927Abstract: A method may include obtaining image data of a subject acquired by an imaging device. The method may also include determining one or more characteristics associated with a body part of the subject from the image data. The one or more characteristics of the body part of the subject may include at least one of position information of the body part in the subject, geometric morphology information of the body part, water content information, or fat content information. The method may also include determining, based on one or more characteristics associated with the body part, values of one or more individualized parameters corresponding to the subject. The method may further include causing the imaging device to perform an imaging scan on the subject according to the values of the one or more individualized parameters.Type: GrantFiled: February 13, 2020Date of Patent: April 26, 2022Assignee: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.Inventors: Liu Liu, Guannan Liu
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Patent number: 11152352Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.Type: GrantFiled: March 28, 2019Date of Patent: October 19, 2021Assignee: Intel CorporationInventors: Akm Ahsan, Mark Armstrong, Guannan Liu
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Publication number: 20200312838Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: Akm Ahsan, Mark Armstrong, Guannan Liu
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Publication number: 20200259018Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.Type: ApplicationFiled: February 8, 2019Publication date: August 13, 2020Applicant: Intel CorporationInventors: Said Rami, Hyung-Jin Lee, Saurabh Morarka, Guannan Liu, Qiang Yu, Bernhard Sell, Mark Armstrong
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Publication number: 20200256936Abstract: A method may include obtaining image data of a subject acquired by an imaging device. The method may also include determining one or more characteristics associated with a body part of the subject from the image data. The one or more characteristics of the body part of the subject may include at least one of position information of the body part in the subject, geometric morphology information of the body part, water content information, or fat content information. The method may also include determining, based on one or more characteristics associated with the body part, values of one or more individualized parameters corresponding to the subject. The method may further include causing the imaging device to perform an imaging scan on the subject according to the values of the one or more individualized parameters.Type: ApplicationFiled: February 13, 2020Publication date: August 13, 2020Applicant: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.Inventors: Liu LIU, Guannan LIU
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Publication number: 20200243517Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.Type: ApplicationFiled: January 25, 2019Publication date: July 30, 2020Inventors: Guannan LIU, Akm A. AHSAN, Mark ARMSTRONG, Bernhard SELL
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Patent number: 9983183Abstract: A nanostructure sensing device comprises a semiconductor nanostructure having an outer surface, and at least one of metal or metal-oxide nanoparticle clusters functionalizing the outer surface of the nanostructure and forming a photoconductive nanostructure/nanocluster hybrid sensor enabling light-assisted sensing of a target analyte.Type: GrantFiled: October 19, 2016Date of Patent: May 29, 2018Assignees: University of Maryland, College Park, The United States of America, as represented by the Secretary of Commerce, George Mason University, The George Washington UniversityInventors: Abhishek Motayed, Geetha Aluri, Albert V. Davydov, Mulpuri V. Rao, Vladimir P. Oleshko, Ritu Bajpai, Mona E. Zaghloul, Brian Thomson, Baomei Wen, Ting Xie, Guannan Liu, Ratan Debnath