Patents by Inventor Guannan Liu

Guannan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12205947
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: January 21, 2025
    Assignee: Intel Corporation
    Inventors: Guannan Liu, Akm A. Ahsan, Mark Armstrong, Bernhard Sell
  • Patent number: 11977137
    Abstract: A method may include obtaining image data of a subject acquired by an imaging device. The method may also include determining one or more characteristics associated with a body part of the subject from the image data. The one or more characteristics of the body part of the subject may include at least one of position information of the body part in the subject, geometric morphology information of the body part, water content information, or fat content information. The method may also include determining, based on one or more characteristics associated with the body part, values of one or more individualized parameters corresponding to the subject. The method may further include causing the imaging device to perform an imaging scan on the subject according to the values of the one or more individualized parameters.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: May 7, 2024
    Assignee: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Liu Liu, Guannan Liu
  • Publication number: 20230317720
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Inventors: Guannan LIU, Akm A. AHSAN, Mark ARMSTRONG, Bernhard SELL
  • Patent number: 11728335
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Guannan Liu, Akm A. Ahsan, Mark Armstrong, Bernhard Sell
  • Patent number: 11515424
    Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Said Rami, Hyung-Jin Lee, Saurabh Morarka, Guannan Liu, Qiang Yu, Bernhard Sell, Mark Armstrong
  • Publication number: 20220236348
    Abstract: A method may include obtaining image data of a subject acquired by an imaging device. The method may also include determining one or more characteristics associated with a body part of the subject from the image data. The one or more characteristics of the body part of the subject may include at least one of position information of the body part in the subject, geometric morphology information of the body part, water content information, or fat content information. The method may also include determining, based on one or more characteristics associated with the body part, values of one or more individualized parameters corresponding to the subject. The method may further include causing the imaging device to perform an imaging scan on the subject according to the values of the one or more individualized parameters.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 28, 2022
    Applicant: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Liu LIU, Guannan LIU
  • Patent number: 11313927
    Abstract: A method may include obtaining image data of a subject acquired by an imaging device. The method may also include determining one or more characteristics associated with a body part of the subject from the image data. The one or more characteristics of the body part of the subject may include at least one of position information of the body part in the subject, geometric morphology information of the body part, water content information, or fat content information. The method may also include determining, based on one or more characteristics associated with the body part, values of one or more individualized parameters corresponding to the subject. The method may further include causing the imaging device to perform an imaging scan on the subject according to the values of the one or more individualized parameters.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: April 26, 2022
    Assignee: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Liu Liu, Guannan Liu
  • Patent number: 11152352
    Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Akm Ahsan, Mark Armstrong, Guannan Liu
  • Publication number: 20200312838
    Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Akm Ahsan, Mark Armstrong, Guannan Liu
  • Publication number: 20200259018
    Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 13, 2020
    Applicant: Intel Corporation
    Inventors: Said Rami, Hyung-Jin Lee, Saurabh Morarka, Guannan Liu, Qiang Yu, Bernhard Sell, Mark Armstrong
  • Publication number: 20200256936
    Abstract: A method may include obtaining image data of a subject acquired by an imaging device. The method may also include determining one or more characteristics associated with a body part of the subject from the image data. The one or more characteristics of the body part of the subject may include at least one of position information of the body part in the subject, geometric morphology information of the body part, water content information, or fat content information. The method may also include determining, based on one or more characteristics associated with the body part, values of one or more individualized parameters corresponding to the subject. The method may further include causing the imaging device to perform an imaging scan on the subject according to the values of the one or more individualized parameters.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 13, 2020
    Applicant: SHANGHAI UNITED IMAGING HEALTHCARE CO., LTD.
    Inventors: Liu LIU, Guannan LIU
  • Publication number: 20200243517
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 30, 2020
    Inventors: Guannan LIU, Akm A. AHSAN, Mark ARMSTRONG, Bernhard SELL
  • Patent number: 9983183
    Abstract: A nanostructure sensing device comprises a semiconductor nanostructure having an outer surface, and at least one of metal or metal-oxide nanoparticle clusters functionalizing the outer surface of the nanostructure and forming a photoconductive nanostructure/nanocluster hybrid sensor enabling light-assisted sensing of a target analyte.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: May 29, 2018
    Assignees: University of Maryland, College Park, The United States of America, as represented by the Secretary of Commerce, George Mason University, The George Washington University
    Inventors: Abhishek Motayed, Geetha Aluri, Albert V. Davydov, Mulpuri V. Rao, Vladimir P. Oleshko, Ritu Bajpai, Mona E. Zaghloul, Brian Thomson, Baomei Wen, Ting Xie, Guannan Liu, Ratan Debnath