Abstract: An amplifier includes a first transmission line from a first terminal to a second terminal. The first transmission line is characterized by a first characteristic impedance matched to a resistance of a source from which a first signal is coupled to the second terminal. The amplifier includes a first resistor with a first resistance and a second resistor with a second resistance coupled between the second terminal and a third terminal. The first resistance and the second resistance are adjustable to match an input impedance at the second terminal to the first characteristic impedance and to tune a gain of a second signal at the third terminal over the first signal at the second terminal. The amplifier includes a second transmission line from the third terminal to a third resistor with a third resistance, the second transmission line being characterized by a second characteristic impedance matched to the third resistance.

Abstract: In some implementations, a circuitry may include a series of symmetrical stages with an initial stage in the series coupled to an input signal having a first plurality of phases and an output stage in the series coupling an output signal comprising a second plurality of phases to a calibration engine, where a quantity of the phases in the output signal is increased based at least on a quantity of the symmetrical stages and a quantity of the first plurality of the phases in the input signal. In addition, the circuitry may include implementations, where the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. The circuitry may include implementations, where the calibration engine outputs a current provided to the series, where the output current can be based at least on a calibrated frequency.

Abstract: Systems and methods are related to a distributed amplification. An amplification device can include cells including a first cell and a second cell and transmission lines including a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and second input coupled to the second line. The summer is configured to provide an output signal.

Abstract: A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.

Abstract: A system including a source follower circuit is disclosed. The source follower circuit configured as a voltage buffer that includes a first common-drain transistor that passes an input signal at the gate to an output loading capacitor at the source, and a second common-drain transistor that is used as a bias current source. The source follower circuit includes a first resistor at the drain of the first transistor generating a first voltage that is fed back through a first path through the gate of the second transistor so as to produce additional current to help the output signal catch up with the input voltage. The source follower circuit further includes an inductive element and bias circuit, which along with the first resistor, increases bandwidth and reduced settling time.

Abstract: Described herein are systems and methods related to a device including an analog-to-digital converter (DAC) configured to convert a digital signal into an analog signal. The systems and methods can receive an analog signal at a first input, and provide the analog signal to a first output in response to a first clock signal. The first clock signal has a level at least partially dependent on the analog signal. The systems and methods can provide a path to a ground node for the first clock signal in response to a second clock signal. The second clock signal is independent of the analog signal.

Abstract: An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.

Abstract: Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.

Abstract: A system including a source follower circuit is disclosed. The source follower circuit configured as a voltage buffer that includes a first common-drain transistor that passes an input signal at the gate to an output loading capacitor at the source, and a second common-drain transistor that is used as a bias current source. The source follower circuit includes a first resistor at the drain of the first transistor generating a first voltage that is fed back through a first path through the gate of the second transistor so as to produce additional current to help the output signal catch up with the input voltage. The source follower circuit further includes an inductive element and bias circuit, which along with the first resistor, increases bandwidth and reduced settling time.

Abstract: Systems and methods are related to a distributed amplification. An amplification device can include cells including a first cell and a second cell and transmission lines including a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and second input coupled to the second line. The summer is configured to provide an output signal.

Abstract: A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.

Abstract: Systems and methods disclosed herein provide a coupled T-coil circuit for differential mode bandwidth extension and common mode rejection. The coupled T-coil circuit includes a first layer including at least a first portion of a first T-coil circuit and a first portion of a second T-coil circuit, and a second layer disposed on top of the first layer and interconnected to the first layer, the second layer including at least a second portion of the first T-coil circuit and a second portion of the second T-coil circuit. The first T-coil circuit includes one or more first coils with a first wind direction. The second T-coil circuit comprises one or more second coils with a second wind direction. The first wind direction can be opposite the second wind direction.

Abstract: A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.

Abstract: A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.

Abstract: A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.

Abstract: The present invention is directed to a distributed dual-band oscillator suitable for low-phase-noise applications. The invention is configured to switch between the odd and even resonant modes of a fourth-order resonator. The switches used for mode selection do not conduct current and therefore do not affect the quality factor (Q) of the resonator. The benefit of this feature is relatively low phase noise.

Abstract: A VCO includes a transformer-based resonator that has a first LC tank and a second LC tank. The resonator has an even resonant mode and an odd resonant mode. The VCO further includes an active transconductance network that is coupled to a two-terminal port of the first tank and is also coupled to a two-terminal port of the second tank. A first terminal of the port of the first tank is capacitively coupled to a first terminal of the port of the second tank. A second terminal of the port of the first tank is capacitively coupled to a second terminal of the port of the second tank. The active transconductance network causes the resonator to resonate in a selectable one of the even and odd resonant modes depending on a digital control signal. The VCO is fine tuned by changing the capacitances of capacitors of the tanks.

Abstract: A VCO includes a transformer-based resonator that has a first LC tank and a second LC tank. The resonator has an even resonant mode and an odd resonant mode. The VCO further includes an active transconductance network that is coupled to a two-terminal port of the first tank and is also coupled to a two-terminal port of the second tank. A first terminal of the port of the first tank is capacitively coupled to a first terminal of the port of the second tank. A second terminal of the port of the first tank is capacitively coupled to a second terminal of the port of the second tank. The active transconductance network causes the resonator to resonate in a selectable one of the even and odd resonant modes depending on a digital control signal. The VCO is fine tuned by changing the capacitances of capacitors of the tanks.