Patents by Inventor Guanyu Luo
Guanyu Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230207461Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric material and a conductive feature extending through the dielectric material. The conductive feature includes a conductive material and has a first top surface. The structure further includes a dummy conductive feature disposed adjacent the conductive feature in the dielectric material, and the dummy conductive feature has a second top surface substantially co-planar with the first top surface. An air gap is formed in the dummy conductive feature.Type: ApplicationFiled: March 7, 2023Publication date: June 29, 2023Inventors: Shu-Wei LI, Guanyu LUO, Shin-Yi YANG, Ming-Han LEE
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Patent number: 11682620Abstract: A structure may include an interconnect-level dielectric layer containing a dielectric material and overlying a substrate, and a metal interconnect structure embedded in the interconnect-level dielectric layer and including a graded metallic alloy layer and a metallic fill material portion. The graded metallic alloy layer includes a graded metallic alloy of a first metallic material and a second metallic material. The atomic concentration of the second metallic material increases with a distance from an interface between the graded metallic alloy and the interconnect-level dielectric layer. The graded metallic alloy layer may be formed by simultaneous or cyclical deposition of the first metallic material and the second metallic material. The first metallic material may provide barrier property, and the second metallic material may provide adhesion property.Type: GrantFiled: March 18, 2021Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shu-Wei Li, Guanyu Luo, Shin-Yi Yang, Ming-Han Lee
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Publication number: 20230187294Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.Type: ApplicationFiled: March 21, 2022Publication date: June 15, 2023Inventors: Ming-Che Lee, Kuo-Ming Wu, Sheng-Chau Chen, Hau-Yi Hsiao, Guanyu Luo, Ping-Tzu Chen, Cheng-Yuan Tsai
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Patent number: 11605591Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric material and a conductive feature extending through the dielectric material. The conductive feature includes a conductive material and has a first top surface. The structure further includes a dummy conductive feature disposed adjacent the conductive feature in the dielectric material, and the dummy conductive feature has a second top surface substantially co-planar with the first top surface. An air gap is formed in the dummy conductive feature.Type: GrantFiled: March 30, 2021Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Wei Li, Guanyu Luo, Shin-Yi Yang, Ming-Han Lee
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Publication number: 20220375791Abstract: A semiconductor device includes a first underlying metal line and a second underlying metal line in a first dielectric layer over a substrate. The semiconductor device includes a first metal feature and a second metal feature in a second dielectric layer over the first dielectric layer. The first metal feature is over and connected to the first underlying metal line, and the second metal feature is over and connected to the second underlying metal line. The first metal feature has a first dimension, the second metal feature has a second dimension, the second dimension being greater than the first dimension. The first metal feature includes a first metal having a first mean free path, the second metal feature includes a second metal having a second mean free path, and the second mean free path is greater than the first mean free path.Type: ApplicationFiled: July 28, 2022Publication date: November 24, 2022Inventors: Guanyu LUO, Shin-Yi YANG, Ming-Han LEE, Shau-Lin SHUE
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Patent number: 11482451Abstract: A method includes receiving an integrated circuit (IC) layout having a plurality of metal features in a metal layer. The method also includes classifying the plurality of metal features into a first type of metal features and a second type of metal features based on a dimensional criterion, where the first type of the metal features have dimensions greater than the second type of the metal features. The method further includes assigning to the first type of metal features a first metal material, and to the second type of metal features a second metal material, where the second metal material is different from the first metal material. The method additionally includes forming the plurality of metal features embedded within a dielectric layer, where each of the plurality of metal features have the respective assigned metal materials.Type: GrantFiled: November 20, 2020Date of Patent: October 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guanyu Luo, Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20220319989Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric material and a conductive feature extending through the dielectric material. The conductive feature includes a conductive material and has a first top surface. The structure further includes a dummy conductive feature disposed adjacent the conductive feature in the dielectric material, and the dummy conductive feature has a second top surface substantially co-planar with the first top surface. An air gap is formed in the dummy conductive feature.Type: ApplicationFiled: March 30, 2021Publication date: October 6, 2022Inventors: Shu-Wei LI, Guanyu LUO, Shin-Yi YANG, Ming-Han LEE
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Publication number: 20220302039Abstract: A structure may include an interconnect-level dielectric layer containing a dielectric material and overlying a substrate, and a metal interconnect structure embedded in the interconnect-level dielectric layer and including a graded metallic alloy layer and a metallic fill material portion. The graded metallic alloy layer includes a graded metallic alloy of a first metallic material and a second metallic material. The atomic concentration of the second metallic material increases with a distance from an interface between the graded metallic alloy and the interconnect-level dielectric layer. The graded metallic alloy layer may be formed by simultaneous or cyclical deposition of the first metallic material and the second metallic material. The first metallic material may provide barrier property, and the second metallic material may provide adhesion property.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Inventors: Shu-Wei LI, Guanyu LUO, Shin-Yi YANG, Ming-Han LEE
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Publication number: 20220165617Abstract: A method includes receiving an integrated circuit (IC) layout having a plurality of metal features in a metal layer. The method also includes classifying the plurality of metal features into a first type of metal features and a second type of metal features based on a dimensional criterion, where the first type of the metal features have dimensions greater than the second type of the metal features. The method further includes assigning to the first type of metal features a first metal material, and to the second type of metal features a second metal material, where the second metal material is different from the first metal material. The method additionally includes forming the plurality of metal features embedded within a dielectric layer, where each of the plurality of metal features have the respective assigned metal materials.Type: ApplicationFiled: November 20, 2020Publication date: May 26, 2022Inventors: Guanyu LUO, Shin-Yi YANG, Ming-Han LEE, Shau-Lin SHUE
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Publication number: 20210407852Abstract: A semiconductor device includes an interconnect structure embedded in a first metallization layer comprising a dielectric material. The interconnect structure includes a first metal material. The semiconductor device includes a first liner structure embedded in the first metallization layer. The first liner structure is extended along one or more boundaries of the interconnect structure in the first metallization layer. The first liner structure includes a second metal material reacted with one or more dopants, the second metal material being different from the first metal material.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Inventors: Ching-Fu Yeh, Yu-Chen Chan, Guanyu Luo, Meng-Pei Lu, Chao-Hsien Peng, Shin-Yi Yang, Ming-Han Lee, Andy Li
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Patent number: 11114374Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a graphene layer between the second contact feature and the first contact feature.Type: GrantFiled: August 22, 2019Date of Patent: September 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shin-Yi Yang, Guanyu Luo, Chin-Lung Chung, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20210057335Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a graphene layer between the second contact feature and the first contact feature.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Inventors: Shin-Yi Yang, Guanyu Luo, Chin-Lung Chung, Ming-Han Lee, Shau-Lin Shue