Patents by Inventor Guarav Khanna

Guarav Khanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10162687
    Abstract: A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Eugene Gorbatov, Alon Naveh, Inder M. Sodhi, Ganapati N. Srinivasa, Eliezer Weissmann, Guarav Khanna, Mishali Naik, Russell J. Fenger, Andrew D. Henroid, Dheeraj R. Subbareddy, David A. Koufaty, Paolo Narvaez
  • Publication number: 20160077576
    Abstract: Technologies for collaborative hardware-software power management include a computing device having a processor that supports a low-power idle state. The low-power idle state may be connected standby or a low-power audio playback state. The computing device detects a present usage scenario and determines whether the usage scenario qualifies for a power boost. Qualifying usage scenarios may include low-power audio playback, screen-on interactive use, and I/O-bound workloads. For qualifying usage scenarios, the computing device applies a boosted power management policy that increases power consumption and performance compared to a default power management policy. The default power management policy may base performance and power consumption on recent processor utilization. The computing device may generate one or more hardware hints to increase performance and power consumption, such as increasing the processor p-state or setting the value of an energy performance bias register.
    Type: Application
    Filed: September 17, 2014
    Publication date: March 17, 2016
    Inventors: Abhinav R. Karhu, Guarav Khanna, Russell J. Fenger
  • Publication number: 20140189301
    Abstract: A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Eugene Gorbatov, Alon Naveh, Inder M. Sodhi, Ganapati N. Srinivasa, Eliezer Weissmann, Guarav Khanna, Mishali Naik, Russell J. Fenger, Andrew D. Henroid, Dheeraj R. Subbareddy, David A. Koufaty, Paolo Narvaez
  • Publication number: 20140181830
    Abstract: According to one embodiment, a processor includes a plurality of processor cores for executing a plurality of threads, a shared storage communicatively coupled to the plurality of processor cores, a power control unit (PCU) communicatively coupled to the plurality of processors to determine, without any software (SW) intervention, if a thread being performed by a first processor core should be migrated to a second processor core, and a migration unit, in response to receiving an instruction from the PCU to migrate the thread, to store at least a portion of architectural state of the first processor core in the shared storage and to migrate the thread to the second processor core, without any SW intervention, such that the second processor core can continue executing the thread based on the architectural state from the shared storage without knowledge of the SW.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Inventors: Mishali Naik, Ganapati N. Srinivasa, Alon Naveh, Inder M. Sodhi, Paolo Narvaez, Eugene Gorbatov, Eliezer Weissmann, Andrew D. Henroid, Andrew J. Herdrich, Guarav Khanna, Scott D. Hahn, Paul Brett, David A. Koufaty, Dheeraj R. Subbareddy, Abirami Prabhakaran