Patents by Inventor Guarav Verma

Guarav Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8528608
    Abstract: A pressure gauge may be coupled to a vessel into which a liquid chemical is to be dispensed. The volume of the vessel may be known and a control device may determine an initial pressure of the vessel using the pressure gauge. A volume of liquid chemical may be dispensed into the vessel which may cause the pressure within the vessel to increase to a second pressure. The control device may determine the second pressure using the pressure gauge may calculate the volume of liquid chemical dispensed into the vessel using the volume of the vessel, the initial pressure of the vessel, and the second pressure of the vessel.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: September 10, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Rajesh Kelekar, Guarav Verma, Kurt Weiner
  • Patent number: 8501505
    Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: August 6, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Guarav Verma, Tony P. Chiang, Imran Hashim, Sandra G. Malhotra, Prashant B. Phatak, Kurt H. Weiner
  • Patent number: 8383430
    Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: February 26, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Guarav Verma, Tony P. Chiang, Imran Hashim, Sandra G Malhotra, Prashant B Phatak, Kurt H Weiner
  • Patent number: 7546573
    Abstract: In one embodiment, a computer system a processor and a memory module comprising logic instructions stored on a computer readable medium which. When executed, the logic instructions configure a processor to create a reticle pattern for use in a lithography process, apply an orthogonalization process to the reticle pattern to create an orthogonalized reticle pattern, and use the orthogonalized reticle pattern in an optical proximity correction process.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: June 9, 2009
    Assignee: KLA-Tencor Corporation
    Inventors: Guarav Verma, Rui-Fang Shi
  • Patent number: 5908307
    Abstract: Pre-amorphization of a surface layer of crystalline silicon to an ultra-shallow (e.g., less than 100 nm) depth provides a solution to fabrication problems including (1) high thermal conduction in crystalline silicon and (2) shadowing and diffraction-interference effects by an already fabricated gate of a field-effect transistor on incident laser radiation. Such problems, in the past, have prevented prior-art projection gas immersion laser doping from being effectively employed in the fabrication of integrated circuits comprising MOS field-effect transistors employing 100 nm and shallower junction technology.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: June 1, 1999
    Assignee: Ultratech Stepper, Inc.
    Inventors: Somit Talwar, Karl-Josef Kramer, Guarav Verma, Kurt Weiner
  • Patent number: 5888888
    Abstract: The method of this invention produces a silicide region on a silicon body that is useful for a variety of purposes, including the reduction of the electrical contact resistance to the silicon body or an integrated electronic device formed thereon. The invented method includes the steps of producing an amorphous region on the silicon body using ion implantation, for example, forming or positioning a metal such as titanium, cobalt or nickel in contact with the amorphous region, and irradiating the metal with intense light from a laser source, for example, to cause metal atoms to diffuse into the amorphous region. The amorphous region thus becomes an alloy region with the desired silicide composition. Upon cooling after irradiation, the alloy region becomes partially crystalline. To convert the alloy region into a more crystalline form, the invented method preferably includes a step of treating the alloy region using rapid thermal annealing, for example.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: March 30, 1999
    Assignee: Ultratech Stepper, Inc.
    Inventors: Somit Talwar, Guarav Verma, Karl-Josef Kramer, Kurt Weiner